MachXO5™-NX

Advanced Secure Control FPGA

MachXO5-NX is Lattice’s secure control FPGA product family. Known for features such as embedded flash, high I/O, and best-in-class security, Lattice’s secure control FPGAs are widely used for system control and management applications in the Compute, Communications, and Industrial market segments. MachXO5-NX improves upon previous generations with higher logic density, faster interfaces, larger internal memory, and enhanced security features enabling more complex board management designs.

Higher Density, More Memory for Complex Control Applications – Up to 100K logic density, 7.3Mb internal memory , and 55Mb dedicated user flash memory (UFM).

Fast and Proven I/O Capabilities – Consistent robust I/O operation as previous generation, 1.0V I/O supporting modern CPU, high speed LVDS, MIPI and PCIe interfaces.

Device Security Protects Intellectual Property – Internal flash configuration, AES256 bitstream encryption, ECC256 bitstream authentication, configuration port lock, and run-time security

Features

  • 25K, 55K, and 100K logic cell density and up to 299 I/O pins
  • MachXO5T devices (55K and 100K LC) support PCIe Gen2.
  • Up to 55 Mbits of dedicated user flash memory (UFM) and on-chip multi-boot configuration
  • Secure FPGA design using ECDSA bitstream authentication and AES256 encryption
  • Low power, high reliability, and support for ADC and DSP on the Lattice Nexus™ Platform

Jump to

Family Table

MachXO5-NX Device Selection Guide
Features MachXO5-NX MachXO5T-NX
Devices LFMXO5-25 LFMXO5-55T LFMXO5-100T
Logic Cells
25k
53k 96k
Embedded Memory (EBR) Blocks (18 kb) 80 166 208
Embedded Memory (EBR) Bits (kb) 1440 2988 3744
Distributed RAM Bits (kb) 184 320 639
Large Memory (LRAM) Blocks 1 5 7
Large Memory (LRAM) Bits (kb) 512 2560 3584
18 X 18 Multipliers 20 146 156
ADC Blocks 2 2 2
450 MHz High Frequency Oscillator 1 1 1
128 kHz Low Power Oscillator 1 1 1
PCIe Gen2 hard IP 0 1 1
GPLL 2 4 4
UFM* (kb) 15360 79872 79872
0.8 mm Pitch Packages & SERDES / Total I/O (Wide Range GPIO / High Performance GPIOs) / Dedicated ADC pins

LFMXO5-25 LFMXO5-55T LFMXO5-100T
256 BBG (14 mm × 14 mm, 0.8 mm) 0 / 199 (159/40) / 6 - -
400 BBG (17 mm × 17 mm, 0.8 mm) 0 / 299 (251/48) / 6 2 / 291 (159/132) / 6 2 / 291 (159/132) / 6

*Without memory initialization

Block Diagram

MachXO5-NX

  • Up to 100K logic cells, 7.3Mb embedded memory , and 55Mb dedicated user flash memory (UFM)
  • MachXO5T devices (55K & 100K LC) support PCIe Gen2 and LPDDR4
  • Up to 299 programmable I/O supporting 1.0/1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Protects intellectual property with bitstream encryption and authentication

Example Applications

Application – Network Switch

  • Aggregates control signals over PCIe
  • Offload real-time monitoring and management of SFPs from network CPU

Application – Hardware Management

  • Easily integrate hardware management functions into MachXO5-NX and L-ASC10
  • High I/O and multiple voltage level support simplify I/O bridging and expansion

Application – LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module

  • Supports LVDS Tunneling Protocol & Interface (LTPI) to aggregate low-speed serial interfaces
  • Enables server architecture that uses secure control modules
  • LTPI is also supported by MachXO3, MachXO3D and Mach-NX

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Package Diagrams
FPGA-DS-02053 7.4 6/22/2023 PDF 10 MB
MachXO5-NX 100K Pinout
FPGA-SC-02049 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 55K Pinout
FPGA-SC-02048 1.0 4/18/2023 CSV 21.8 KB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.5 7/5/2022 PDF 3.1 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.3 5/31/2022 PDF 1.4 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.2 2/17/2023 PDF 1.7 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.4 6/7/2022 PDF 1.9 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 1.9 2/28/2023 PDF 1.4 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
ADC User Guide for Nexus Platform
FPGA-TN-02129 1.7 9/4/2023 PDF 1.2 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.5 4/18/2023 PDF 751.6 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.3 4/18/2023 PDF 868.5 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.2 4/24/2023 PDF 1.9 MB
MachXO5-NX Hardware Checklist
FPGA-TN-02274 1.1 4/18/2023 PDF 970.8 KB
MachXO5-NX 25K Pinout
FPGA-SC-02038 1.0 5/26/2023 CSV 16.9 KB
MachXO5-NX High-Speed I/O Interface
FPGA-TN-02286 0.83 5/31/2023 PDF 3.5 MB
MachXO5-NX Family Data Sheet
FPGA-DS-02102 1.4 5/23/2023 PDF 2.1 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.3 12/5/2022 PDF 1.2 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.7 12/5/2022 PDF 812.2 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.1 12/5/2022 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 4.5 4/18/2023 PDF 926 KB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
Using TraceID
FPGA-TN-02084 2.5 1/25/2023 PDF 400.6 KB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 1.3 9/12/2023 PDF 2.1 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 1.4 9/12/2023 PDF 2.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX Family Data Sheet
FPGA-DS-02102 1.4 5/23/2023 PDF 2.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Advanced Configuration Security Usage Guide for Nexus Platform
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6055 for detail instruction
FPGA-TN-02176 1/12/2023 WEB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.5 7/5/2022 PDF 3.1 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.3 5/31/2022 PDF 1.4 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.2 2/17/2023 PDF 1.7 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.4 6/7/2022 PDF 1.9 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 1.9 2/28/2023 PDF 1.4 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
ADC User Guide for Nexus Platform
FPGA-TN-02129 1.7 9/4/2023 PDF 1.2 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.5 4/18/2023 PDF 751.6 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.3 4/18/2023 PDF 868.5 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.2 4/24/2023 PDF 1.9 MB
MachXO5-NX Hardware Checklist
FPGA-TN-02274 1.1 4/18/2023 PDF 970.8 KB
MachXO5-NX High-Speed I/O Interface
FPGA-TN-02286 0.83 5/31/2023 PDF 3.5 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.3 12/5/2022 PDF 1.2 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.7 12/5/2022 PDF 812.2 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.1 12/5/2022 PDF 6.2 MB
Thermal Management
FPGA-TN-02044 4.5 4/18/2023 PDF 926 KB
Using TraceID
FPGA-TN-02084 2.5 1/25/2023 PDF 400.6 KB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 1.3 9/12/2023 PDF 2.1 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 1.4 9/12/2023 PDF 2.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Package Diagrams
FPGA-DS-02053 7.4 6/22/2023 PDF 10 MB
MachXO5-NX 100K Pinout
FPGA-SC-02049 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 55K Pinout
FPGA-SC-02048 1.0 4/18/2023 CSV 21.8 KB
MachXO5-NX 25K Pinout
FPGA-SC-02038 1.0 5/26/2023 CSV 16.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-02005 7.6 4/27/2023 ZIP 4.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Product Selector Guide
I0211 38.0 4/18/2023 PDF 7.1 MB
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DC-SCM Implementation in Lattice FPGA
WP0031 2.0 3/22/2023 PDF 587.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[BSDL] LFMXO5-100
FPGA-MD-02043 1.14 4/18/2023 BSM 63.4 KB
[BSDL] LFMXO5-25
FPGA-MD-02027 1.14 5/31/2022 ZIP 18.9 KB
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MachXO5-NX Device Family Delphi Models
FPGA-MD-02031 1.2 7/5/2023 ZIP 22.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[IBIS] MachXO5-NX
FPGA-MD-02035 1.1 4/18/2023 ZIP 14.8 MB

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