MachXO5™-NX

Advanced Secure Control FPGA

MachXO5-NX is Lattice’s fifth generation secure control FPGA product family. Known for features such as embedded flash, high I/O, and best-in-class security, Lattice’s secure control FPGAs are widely used for system control and management applications in the Compute, Communications, and Industrial market segments. MachXO5-NX improves upon previous generations with higher logic density, faster interfaces, larger internal memory, and security features enabling more complex board management designs.

Higher Density, More Memory for Complex Control Applications – 25k logic density, 1.9 Mb of embedded memory, and 9.2 Mb of user flash memory.

Fast and Proven I/O Capabilities – Consistent robust I/O operation as previous generation, 1.0 V I/O supporting modern CPU, high speed LVDS and MIPI interfaces.

Device Security Protects Intellectual Property – Internal flash configuration, AES256 bitstream encryption, ECC256 bitstream authentication, configuration port lock, and run-time security.

Features

  • 25k LC logic density and up to 300 I/O pins
  • 9.2 Mbits of user flash memory and on-chip multi-boot configuration
  • Secure FPGA design using ECDSA bitstream authentication and AES256 encryption
  • Supported by Lattice Radiant® and Lattice Propel™
  • Low power, high reliability, and support for ADC and DSP on the Lattice Nexus™ Platform

Jump to

Family Table

MachXO5-NX Device Selection Guide
Features LFMXO5-25
Logic Cells
25k
Embedded Memory (EBR) Blocks (18 kb) 80
Embedded Memory (EBR) Bits (kb) 1440
Distributed RAM Bits (kb) 184
Distributed RAM Bits (kb) 184
Large Memory (LRAM) Blocks 1
Large Memory (LRAM) Bits (kb) 512
18 X 18 Multipliers 20
ADC Blocks 2
450 MHz High Frequency Oscillator 1
128 kHz Low Power Oscillator 1
GPLL 2
UFM (kb) 15360
0.8 mm Pitch Packages & Total I/O / (Wide Range GPIO / High Performance GPIOs / Dedicated ADC pins)

LFMXO5-25
256 BBG (14 mm × 14 mm, 0.8 mm) 206 (160/40/6)
400 BBG (17 mm × 17 mm, 0.8 mm) 306 (252/48/6)

Block Diagram

  • Up to 25k logic cells, 1.9 Mbits of memory and 9.2 Mbits of dedicated user flash memory
  • Up to 300 programmable I/O supporting 1.0/1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Protects intellectual property with bitstream encryption and authentication
  • Low power, low SER, supporting SGMII and ADC interfaces

Example Applications

Application – Hardware Management

  • Easily integrate hardware management functions into MachXO5-NX and L-ASC10
  • High I/O and multiple voltage level support simplify I/O bridging and expansion

Application – LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module

  • Supports LVDS Tunneling Protocol & Interface (LTPI) to aggregate low-speed serial interfaces
  • Enables server architecture that uses secure control modules
  • LTPI is also supported by MachXO3, MachXO3D and Mach-NX

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX 25K Pinout
FPGA-SC-02038 .9 5/31/2022 CSV 16.8 KB
MachXO5-NX High-Speed I/O Interface
FPGA-TN-02286 .8 5/31/2022 PDF 3.7 MB
MachXO5-NX Family Data Sheet
FPGA-DS-02102 .8 5/31/2022 PDF 3.4 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 1.0 5/31/2022 PDF 2.5 MB
Using TraceID
FPGA-TN-02084 2.3 5/31/2022 PDF 377.7 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.1 6/16/2022 PDF 1.5 MB
Package Diagrams
FPGA-DS-02053 7.0 6/7/2022 PDF 9.5 MB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.5 7/5/2022 PDF 3.1 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.3 5/31/2022 PDF 1.4 MB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.4 6/7/2022 PDF 1.9 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 1.6 6/7/2022 PDF 1.5 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
ADC Usage Guide for Nexus Platform
FPGA-TN-02129 1.4 5/31/2022 PDF 1.9 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 1.5 5/31/2022 PDF 1 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.4 6/9/2022 PDF 1.3 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.2 6/7/2022 PDF 865.6 KB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.5 4/11/2022 PDF 388.7 KB
Thermal Management
FPGA-TN-02044 4.2 6/7/2022 PDF 1.3 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.0 6/7/2022 PDF 2.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.9 8/1/2022 PDF 6.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX Family Data Sheet
FPGA-DS-02102 .8 5/31/2022 PDF 3.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX High-Speed I/O Interface
FPGA-TN-02286 .8 5/31/2022 PDF 3.7 MB
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 1.0 5/31/2022 PDF 2.5 MB
Using TraceID
FPGA-TN-02084 2.3 5/31/2022 PDF 377.7 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.1 6/16/2022 PDF 1.5 MB
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.5 7/5/2022 PDF 3.1 MB
High-Speed PCB Design Considerations
FPGA-TN-02178 6.3 5/31/2022 PDF 1.4 MB
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.4 6/7/2022 PDF 1.9 MB
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 1.6 6/7/2022 PDF 1.5 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022 PDF 1.4 MB
ADC Usage Guide for Nexus Platform
FPGA-TN-02129 1.4 5/31/2022 PDF 1.9 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 1.5 5/31/2022 PDF 1 MB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.4 6/9/2022 PDF 1.3 MB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.2 6/7/2022 PDF 865.6 KB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.5 4/11/2022 PDF 388.7 KB
Thermal Management
FPGA-TN-02044 4.2 6/7/2022 PDF 1.3 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.0 6/7/2022 PDF 2.4 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.9 8/1/2022 PDF 6.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX 25K Pinout
FPGA-SC-02038 .9 5/31/2022 CSV 16.8 KB
Package Diagrams
FPGA-DS-02053 7.0 6/7/2022 PDF 9.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022 PDF 1.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-02005 7.4 6/1/2022 ZIP 4.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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DC-SCM Implementation in Lattice FPGA
WP0031 1.0 5/31/2022 PDF 628.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
[BSDL] LFMXO5-25
FPGA-MD-02027 1.14 5/31/2022 ZIP 18.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX Device Family Delphi Models
FPGA-MD-02031 .8 5/31/2022 ZIP 17.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
[IBIS] MachXO5-NX
FPGA-MD-02035 1.0 5/31/2022 ZIP 10.8 MB

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