Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support














Tags

































Providers
Clear All
  • Flash Access IP Core

    IP Core

    Flash Access IP Core

    Flash Access IP Core performs write and read access through the LMMI interface.
    Flash Access IP Core
  • Internal Flash Controller IP Core

    IP Core

    Internal Flash Controller IP Core

    Internal Flash Controller enables you to access the internal Flash Memory using the AHB-Lite or APB interface.
    Internal Flash Controller IP Core
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • Watchdog Timer IP Core

    IP Core

    Watchdog Timer IP Core

    Watchdog Timer IP Core is a two-stage timer that will start to count depending on the computer status.
    Watchdog Timer IP Core
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    Tri-Speed Ethernet MAC IP Core
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
    UART 16550 IP Core
  • RGMII to GMII Bridge Reference Design

    Reference Design

    RGMII to GMII Bridge Reference Design

    Provides a bi-directional bridge function for transferring data between RGMII and GMII
    RGMII to GMII Bridge Reference Design
  • FFT Compiler

    IP Core

    FFT Compiler

    Can be configured to perform forward FFT, inverse FFT (IFFT) or port selectable forward/inverse FFT. High-performance streaming and low-resource burst modes.
    FFT Compiler
  • FIR Filter Generator

    IP Core

    FIR Filter Generator

    Highly configurable, multi-channel FIR filter. Supports up to 256 channels each with 2048 taps. Input and coefficient widths from 4 to 32 bits.
    FIR Filter Generator
  • SGMII and Gb Ethernet PCS

    IP Core

    SGMII and Gb Ethernet PCS

    Implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX) specifications
    SGMII and Gb Ethernet PCS
  • CORDIC

    IP Core

    CORDIC

    A simple and efficient algorithm to calculate hyperbolic and trigonometric functions and convert polar co-ordinates to cartesian and vice versa
    CORDIC
  • UART Reference Design

    Reference Design

    UART Reference Design

    Fully configurable UART functionally compatible with the NS16450 UART
    UART Reference Design
  • Divider

    IP Core

    Divider

    A one-clock divider which completes one integer division every clock. It supports signed or unsigned inputs and provides configurable output latency.
    Divider
  • Page 1 of 1
    First Previous
    1
    Next Last