Lattice Blog

FPGA Design Constraints – Performance and Analysis to Achieve Design and Timing Closure

FPGA design constraints - performance and analysis to achieve design and timing closure

Posted 12/15/2021 by Roger Do, Senior Product Manager, Design Tools, Lattice Semiconductor

Traditionally, FPGA design was simple. Designers set a basic clock constraint that was propagated across the chip. But now, FPGA designs have become much more complex. There are multiple clocks, and relationships between those clocks. There may be clock domain crossings that need to be accounted for. So, FPGA design tools today must feature much greater analysis capabilities to show the designer, for example, where those clock domain crossings are, to be able to constrain for multiple clocks, an...

Introducing Lattice Propel

Introducing Lattice Propel

Posted 06/04/2020 by Roger Do

The Lattice Propel design environment lets hardware and software developers quickly and easily develop Lattice FPGA-based applications in minutes.

Lattice Radiant Software

Lattice Radiant Software: Full-featured Tool Suite for Edge Designs

Posted 03/06/2018 by Choon-Hoe Yeoh

We recently introduced our next generation FPGA design software: Lattice Radiant software. Embracing our corporate mission of enabling edge connectivity and computing designs, the Radiant software was specifically created for the development of edge applications. It is a full-featured FPGA design tool suite and yet simple to use.

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