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  • ​​Hyperbus Controller IP Core ​

    IP Core

    ​​Hyperbus Controller IP Core ​

    Citrobits' Hyperram memory controller was strategically designed with user accessibility as a top priority, leveraging the AXI 4 interface, widely adopted in modern system architectures.
    ​​Hyperbus Controller IP Core ​
  • Citrobits HyperRAM™ Reference Design

    Reference Design

    Citrobits HyperRAM™ Reference Design

    Performance-optimized reference design for HyperRAM™ Controller, using Lattice Propel for connecting it via AXI4 to RISC-V for memory intense applications.
    Citrobits HyperRAM™ Reference Design
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