CertusPro-NX

Advanced General Purpose FPGA

10G SERDES at Lowest Power and Smallest Package – Up to 8 SERDES lanes supporting up to 10.3 Gbps per lane, in packages as small as 9x9 mm. Up to 4x lower power vs. similar FPGAs.

More On-chip Memory, and LPDDR4 Support – Up to 7.3 Mb of on-chip memory. Only FPGA in class with LPDDR4 support. LPDDR4, DDR3/3L, LPDDR2 supported at 1066 Mbps.

Built on Lattice Nexus platform – Class-leading power efficiency. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.

CertusPro-NX

Features

  • Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).
  • Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.

Jump to

Family Table

CertusPro-NX Device Selection Guide
Features LFCPNX-50 LFCPNX-100
Logic Cells 52K 96K
Embedded Memory (EBR) Bits (Kb) 1728
3744
Large Memory (LRAM) Bits (Kb) 2048
3584
18 X 18 Multipliers 96
156
ADC Blocks 2
2
GPLL 3
4
PCIe Gen3 Hard IP 1
1
0.5 mm SERDES / Total I/O (Wide Range, High Performance, ADC Dedicated Inputs)

LFCPNX-50 LFCPNX-100
ASG256 (9 x 9 mm) 4 / 170 (TBD) 4 / 165 (75+84+6)
0.8 mm SERDES / Total I/O (Wide Range, High Performance, ADC Dedicated Inputs)

LFCPNX-50 LFCPNX-100
CBG256 (14 x 14 mm) 4 / 170 (TBD) 4 / 165 (75+84+6)
BBG484 (19 x 19 mm) 4 / 230 (TBD) 8 / 305 (167+132+6)
1.0 mm SERDES / Total I/O (Wide Range, High Performance, ADC Dedicated Inputs)

LFCPNX-50 LFCPNX-100
BFG484 (23 x 23 mm) 4 / 230 (TBD) 4 / 305 (167+132+6)
LFG672 (27 x 27 mm) 8 / 305 (167+132+6)

Example Solutions

Smart SFP+ Optical Module

  • Implement enhanced Ethernet functions (e.g., Ethernet demarcation, OAM processing, SLA monitoring, etc.)
  • Compact packages as small as 9x9 mm with 10 Gigabit Ethernet support and 100K Logic Cells
  • Class-leading power efficiency for simpler thermal management
  • Hardened 10 Gigabit Ethernet PCS blocks supporting 10GBASE-R at 10.3125 Gbps, and available Ethernet MAC IP

Control Plane Security and Hardware Management

  • Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and 10GE control plane traffic
  • Security functions (e.g., encryption, authentication) implemented in FPGA helps secure control plane traffic
  • 10G SERDES supporting PCIe Gen 3 x4 (in hard IP) and 10 Gigabit Ethernet (with 10GBASE-R PCS in hard IP)
  • High system reliability and up-time due to 100x lower Soft Error Rate (SER) from FD-SOI technology
  • Fast FPGA configuration supports board management needs and PCIe boot-time requirements

Machine Vision

  • Vision processing and bridging for high performance SLVS-EC sensors
  • 10G SERDES supporting SLVS-EC sensor interface, 10 GigE Vision and CoaXPress
  • 9x9 mm small size package and class-leading power efficiency meets stringent requirements of space and thermal budget constrained camera modules
  • Up to 7.3 Mb on-chip memory for ISP and vision processing
  • LPDDR4 external memory support for optional frame buffering

Frame Grabber

  • Image acquisition, pre-processing and DMA over PCIe to host PC
  • 10G SERDES supporting 10 GigE Vision, CoaXPress and PCIe Gen 3 x4 (in hard IP)
  • Up to 7.3 Mb on-chip memory for video processing / tagging
  • LPDDR4 external memory support for optional frame buffering

Smart Camera AI Processing

  • Offload AI processing and ISP from SoC
  • Interface with popular image sensors over MIPI at up to 1.5 Gbps per lane, using High Performance IO (HPIO)
  • Up to 7.3 Mb on-chip memory and flexible DSP resources to efficiently perform AI processing and ISP
  • LPDDR4 external memory support for frame buffering
  • Flexible output over MIPI or PCIe to SoC to enable smart device with high quality imaging

Videos

CertusPro-NX: Power Consumption ComparisonExpand Image

CertusPro-NX: Power Consumption Comparison

See a competitive power consumption demo comparing the power consumption of a Lattice CertusPro-NX running a 10 Gbps SERDES design with two similar competing FPGAs.
CertusPro-NX: AI/ML Analytics DemonstrationExpand Image

CertusPro-NX: AI/ML Analytics Demonstration

This demonstration highlights the advanced smart vision analytics enabled by a Lattice CertusPro-NX FPGA’s high internal memory density and fast parallel processing architecture.
CertusPro-NX: Reliability ComparisonExpand Image

CertusPro-NX: Reliability Comparison

A leading cause of silicon malfunctions are single event upsets (SEUs) caused by radiation particle strikes. In this competitive demonstration, the reliability of Lattice CertusPro-NX FPGAs when exposed to a stream of alpha particles is compared with two similar competing devices.

Design Resources

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Intellectual Property & Reference Designs

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Software

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Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] CertusPro-NX 100K
FPGA-MD-02025 0.1 6/23/2021 ZIP 42.3 MB
CertusPro-NX Family Data Sheet
FPGA-DS-02086 0.81 9/24/2021 PDF 4.3 MB
Memory Usage Guide for Nexus Platform
FPGA-TN-02094 1.2 6/23/2021 PDF 3.6 MB
Power Management and Calculation for Certus-NX and CertusPro-NX Devices
FPGA-TN-02257 1.0 6/23/2021 PDF 1 MB
sysCLOCK PLL Design and Usage Guide for Nexus Platform
FPGA-TN-02095 1.6 9/23/2021 PDF 1.9 MB
sysDSP Usage Guide for Nexus Platform
FPGA-TN-02096 1.2 6/23/2021 PDF 1.8 MB
sysI/O Usage Guide for Nexus Platform
FPGA-TN-02067 1.3 6/23/2021 PDF 1.3 MB
sysCONFIG Usage Guide for Nexus Platform
FPGA-TN-02099 1.5 9/10/2021 PDF 1.8 MB
CertusPro-NX High-Speed I/O Interface
FPGA-TN-02244 0.81 6/23/2021 PDF 4.4 MB
CertusPro-NX Hardware Checklist
FPGA-TN-02255 0.81 9/6/2021 PDF 470.8 KB
CertusPro-NX SerDes/PCS Usage Guide
FPGA-TN-02245 0.81 6/23/2021 PDF 5.6 MB
ADC Usage Guide for Nexus Platform
FPGA-TN-02129 1.3 6/23/2021 PDF 1.4 MB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.2 6/23/2021 PDF 1.2 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.0 8/11/2021 PDF 1.1 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.3 6/23/2021 PDF 776.5 KB
CertusPro-NX Reinvigorates General-Purpose FPGAs
1.0 6/23/2021 PDF 294.4 KB
CertusPro-NX 100K Pinout
FPGA-SC-02022 0.91 6/23/2021 CSV 28.4 KB
Thermal Management
FPGA-TN-02044 3.8 6/23/2021 PDF 1.6 MB
Using TraceID
FPGA-TN-02084 2.2 6/23/2021 PDF 797.2 KB
Package Diagrams
FPGA-DS-02053 6.6 9/28/2021 PDF 8.5 MB
[BSDL] LFCPNX-100 LFG672
FPGA-MD-02024 1.14 6/23/2021 BSM 73.4 KB
[BSDL] LFCPNX-100 BBG484
FPGA-MD-02024 1.14 6/23/2021 BSM 68.2 KB
[BSDL] LFCPNX-100 ASG256
FPGA-MD-02024 1.14 6/23/2021 BSM 51 KB
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.3 10/25/2021 PDF 566.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
CertusPro-NX Family Data Sheet
FPGA-DS-02086 0.81 9/24/2021 PDF 4.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Advanced Configuration Security Usage Guide for Nexus Platform
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6055 for detail instruction
FPGA-TN-02176 5/14/2021 /SUPPORT/ANSWERDATABASE/6/0/5/6055
Memory Usage Guide for Nexus Platform
FPGA-TN-02094 1.2 6/23/2021 PDF 3.6 MB
Power Management and Calculation for Certus-NX and CertusPro-NX Devices
FPGA-TN-02257 1.0 6/23/2021 PDF 1 MB
sysCLOCK PLL Design and Usage Guide for Nexus Platform
FPGA-TN-02095 1.6 9/23/2021 PDF 1.9 MB
sysDSP Usage Guide for Nexus Platform
FPGA-TN-02096 1.2 6/23/2021 PDF 1.8 MB
sysI/O Usage Guide for Nexus Platform
FPGA-TN-02067 1.3 6/23/2021 PDF 1.3 MB
sysCONFIG Usage Guide for Nexus Platform
FPGA-TN-02099 1.5 9/10/2021 PDF 1.8 MB
CertusPro-NX High-Speed I/O Interface
FPGA-TN-02244 0.81 6/23/2021 PDF 4.4 MB
CertusPro-NX Hardware Checklist
FPGA-TN-02255 0.81 9/6/2021 PDF 470.8 KB
CertusPro-NX SerDes/PCS Usage Guide
FPGA-TN-02245 0.81 6/23/2021 PDF 5.6 MB
ADC Usage Guide for Nexus Platform
FPGA-TN-02129 1.3 6/23/2021 PDF 1.4 MB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.2 6/23/2021 PDF 1.2 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.0 8/11/2021 PDF 1.1 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.3 6/23/2021 PDF 776.5 KB
Thermal Management
FPGA-TN-02044 3.8 6/23/2021 PDF 1.6 MB
Using TraceID
FPGA-TN-02084 2.2 6/23/2021 PDF 797.2 KB
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.3 10/25/2021 PDF 566.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
CertusPro-NX 100K Pinout
FPGA-SC-02022 0.91 6/23/2021 CSV 28.4 KB
Package Diagrams
FPGA-DS-02053 6.6 9/28/2021 PDF 8.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-02005 7.2 10/14/2021 ZIP 4.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Product Selector Guide
I0211 32.0 10/1/2021 PDF 11.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
CertusPro-NX Reinvigorates General-Purpose FPGAs
1.0 6/23/2021 PDF 294.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LFCPNX-100 LFG672
FPGA-MD-02024 1.14 6/23/2021 BSM 73.4 KB
[BSDL] LFCPNX-100 BBG484
FPGA-MD-02024 1.14 6/23/2021 BSM 68.2 KB
[BSDL] LFCPNX-100 ASG256
FPGA-MD-02024 1.14 6/23/2021 BSM 51 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
CertusPro-NX Device Family Delphi Models
FPGA-MD-02026 1.0 9/16/2021 ZIP 35.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] CertusPro-NX 100K
FPGA-MD-02025 0.1 6/23/2021 ZIP 42.3 MB

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