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  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    A reference design for implementing object classification based on Mobilenet NN model running on Lattice CertusPro-NX low power FPGA
    Object Classification Reference Design
  • Lattice ORAN™ Control Reference Design

    Reference Design

    Lattice ORAN™ Control Reference Design

    Lattice ORAN enable secure out-of-band communication over I3C/SMBus/I2C/PCIe and provide crypto-256 and Crypto-384 services to customers through software APIs.
    Lattice ORAN™ Control Reference Design
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • CSI-2/DSI D-PHY Receiver

    IP Core

  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX

    Modular MIPI/D-PHY Reference Design - MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge reference design takes DSI or CSI-2 MIPI data and converts them to OpenLDI format on LVDS.
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX
  • N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX

    Reference Design

    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX

    Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX
  • SLVS-EC to MIPI CSI-2 with CertusPro-NX

    Reference Design

    SLVS-EC to MIPI CSI-2 with CertusPro-NX

    Modular MIPI/D-PHY Reference Design - Support advance camera and display interconnections in mobile devices that enable higher performance sensor with optimized power.
    SLVS-EC to MIPI CSI-2 with CertusPro-NX
  • SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

    Modular MIPI/D-PHY Reference Design - Solves the mismatch between SubLVDS output image sensor and an ISP/AP using CSI-2 interface.
    SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Reference Design

  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • 10Gb Ethernet PCS IP Core

    IP Core

    10Gb Ethernet PCS IP Core

    The 10Gb Ethernet PCS IP Core provides XGMII interface to MAC and follows IEEE802.3 10G Base-R standard.
    10Gb Ethernet PCS IP Core
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