MachXO5™-NX

Advanced Secure Control FPGA

MachXO5-NX is Lattice’s secure control FPGA product family. Known for features such as embedded flash, high I/O, and best-in-class security, Lattice’s secure control FPGAs are widely used for system control and management applications in the Compute, Communications, and Industrial market segments. MachXO5-NX improves upon previous generations with higher logic density, faster interfaces, larger internal memory, and enhanced security features enabling more complex board management designs.

Higher Density, More Memory for Complex Control Applications – Up to 100K logic density, 7.3Mb internal memory , and 55Mb dedicated user flash memory (UFM).

Fast and Proven I/O Capabilities – Consistent robust I/O operation as previous generation, 1.0V I/O supporting modern CPU, high speed LVDS, MIPI and PCIe interfaces.

Device Security Protects Intellectual Property – Internal flash configuration, AES256 bitstream encryption, ECC256 bitstream authentication, configuration port lock, and run-time security

Features

  • 25K, 55K, and 100K logic cell density and up to 299 I/O pins
  • MachXO5T devices (55K and 100K LC) support PCIe Gen2.
  • Up to 55 Mbits of dedicated user flash memory (UFM) and on-chip multi-boot configuration
  • Secure FPGA design using ECDSA bitstream authentication and AES256 encryption
  • Low power, high reliability, and support for ADC and DSP on the Lattice Nexus™ Platform

Jump to

Family Table

MachXO5-NX Device Selection Guide
Features MachXO5-NX MachXO5T-NX
Devices LFMXO5-25 LFMXO5-55T LFMXO5-100T
Logic Cells
25k
53k 96k
Embedded Memory (EBR) Blocks (18 kb) 80 166 208
Embedded Memory (EBR) Bits (kb) 1440 2988 3744
Distributed RAM Bits (kb) 184 320 639
Large Memory (LRAM) Blocks 1 5 7
Large Memory (LRAM) Bits (kb) 512 2560 3584
18 X 18 Multipliers 20 146 156
ADC Blocks 2 2 2
450 MHz High Frequency Oscillator 1 1 1
128 kHz Low Power Oscillator 1 1 1
PCIe Gen2 hard IP 0 1 1
GPLL 2 4 4
UFM* (kb) 15360 79872 79872
0.8 mm Pitch Packages & SERDES / Total I/O (Wide Range GPIO / High Performance GPIOs) / Dedicated ADC pins

LFMXO5-25 LFMXO5-55T LFMXO5-100T
256 BBG (14 mm × 14 mm, 0.8 mm) 0 / 199 (159/40) / 6 - -
400 BBG (17 mm × 17 mm, 0.8 mm) 0 / 299 (251/48) / 6 2 / 291 (159/132) / 6 2 / 291 (159/132) / 6

*Without memory initialization

Block Diagram

MachXO5-NX

  • Up to 100K logic cells, 7.3Mb embedded memory , and 55Mb dedicated user flash memory (UFM)
  • MachXO5T devices (55K & 100K LC) support PCIe Gen2 and LPDDR4
  • Up to 299 programmable I/O supporting 1.0/1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Protects intellectual property with bitstream encryption and authentication

Example Applications

Application – Network Switch

  • Aggregates control signals over PCIe
  • Offload real-time monitoring and management of SFPs from network CPU

Application – Hardware Management

  • Easily integrate hardware management functions into MachXO5-NX and L-ASC10
  • High I/O and multiple voltage level support simplify I/O bridging and expansion

Application – LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module

  • Supports LVDS Tunneling Protocol & Interface (LTPI) to aggregate low-speed serial interfaces
  • Enables server architecture that uses secure control modules
  • LTPI is also supported by MachXO3, MachXO3D and Mach-NX

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
TSE MAC Driver API Reference
FPGA-TN-02341 1.0 12/21/2023
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.4 2/28/2024
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.6 4/19/2024
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 2.2 10/19/2023
sysCONFIG User Guide for Nexus Platform
FPGA-TN-02099 3.0 5/23/2024
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.6 3/19/2024
High-Speed PCB Design Considerations
FPGA-TN-02178 6.3 5/31/2022
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022
ADC User Guide for Nexus Platform
FPGA-TN-02129 1.7 9/4/2023
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.8 2/28/2024
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.4 9/26/2023
Package Diagrams
FPGA-DS-02053 8.0 3/19/2024
MachXO5-NX 100T Pinout
FPGA-SC-02049 1.1 3/6/2024
MachXO5-NX 55K Pinout
FPGA-SC-02048 1.0 4/18/2023
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.5 10/9/2023
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.8 9/26/2023
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.3 12/5/2023
Thermal Management
FPGA-TN-02044 4.9 3/7/2024
Using TraceID
FPGA-TN-02084 2.6 5/19/2024
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.4 10/17/2023
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023
MachXO5-NX Hardware Checklist
FPGA-TN-02274 1.4 5/8/2024
MachXO5-NX 25K Pinout
FPGA-SC-02038 1.0 5/26/2023
MachXO5-NX High-Speed I/O Interface
FPGA-TN-02286 0.84 4/4/2024
MachXO5-NX Family Data Sheet
FPGA-DS-02102 1.6 5/20/2024
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 2.0 5/20/2024
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX Family Data Sheet
FPGA-DS-02102 1.6 5/20/2024
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Signing JEDEC with HSM-Generated Signature
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6848 for detail instruction.
3/13/2024 /SUPPORT/ANSWERDATABASE/6/8/4/6848
Advanced Configuration Security Usage Guide for Nexus Platform
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 6848 for detail instruction
FPGA-TN-02176 1.7 1/12/2023 /SUPPORT/ANSWERDATABASE/6/8/4/6848
TSE MAC Driver API Reference
FPGA-TN-02341 1.0 12/21/2023
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022
sysCLOCK PLL Design and User Guide for Nexus Platform
FPGA-TN-02095 2.4 2/28/2024
sysDSP User Guide for Nexus Platform
FPGA-TN-02096 1.6 4/19/2024
sysI/O User Guide for Nexus Platform
FPGA-TN-02067 2.2 10/19/2023
sysCONFIG User Guide for Nexus Platform
FPGA-TN-02099 3.0 5/23/2024
Memory User Guide for Nexus Platform
FPGA-TN-02094 1.6 3/19/2024
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-02081 1.0 4/3/2024
High-Speed PCB Design Considerations
FPGA-TN-02178 6.3 5/31/2022
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.3 5/31/2022
Adding Scalable Power and Thermal Management to Nexus FPGAs
FPGA-AN-02079 1.0 1/31/2024
ADC User Guide for Nexus Platform
FPGA-TN-02129 1.7 9/4/2023
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.8 2/28/2024
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.4 9/26/2023
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 2.5 10/9/2023
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.8 9/26/2023
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.3 12/5/2023
Thermal Management
FPGA-TN-02044 4.9 3/7/2024
Using TraceID
FPGA-TN-02084 2.6 5/19/2024
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.4 10/17/2023
I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023
I3C Controller Driver API Reference
FPGA-TN-02342 1.0 12/21/2023
MachXO5-NX Hardware Checklist
FPGA-TN-02274 1.4 5/8/2024
MachXO5-NX High-Speed I/O Interface
FPGA-TN-02286 0.84 4/4/2024
MachXO5-NX Programming and Configuration User Guide
FPGA-TN-02271 2.0 5/20/2024
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Package Diagrams
FPGA-DS-02053 8.0 3/19/2024
MachXO5-NX 100T Pinout
FPGA-SC-02049 1.1 3/6/2024
MachXO5-NX 55K Pinout
FPGA-SC-02048 1.0 4/18/2023
MachXO5-NX 25K Pinout
FPGA-SC-02038 1.0 5/26/2023
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Embedded Security and Function Block User Guide for MachXO5-NX Devices
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instruction.
2/21/2024 /SUPPORT/ANSWERDATABASE/6/8/4/6848
Advanced Key Management User Guide for MachXO5-NX
This document would be provided through Technical Support Request. Please refer to Answer Database FAQ 6848 for the detailed instruction.
2/21/2024 /SUPPORT/ANSWERDATABASE/6/8/4/6848
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 5/31/2022
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DC-SCM Implementation in Lattice FPGA
WP0031 2.0 3/22/2023
TITLE NUMBER VERSION DATE FORMAT SIZE
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[BSDL] LFMXO5-100
FPGA-MD-02043 1.14 4/18/2023
[BSDL] LFMXO5-25
FPGA-MD-02027 1.14 5/31/2022
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO5-NX Device Family Delphi Models
FPGA-MD-02031 1.2 7/5/2023
TITLE NUMBER VERSION DATE FORMAT SIZE
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[IBIS] MachXO5-NX
FPGA-MD-02035 1.1 4/18/2023

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