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  • Topic
    ID
    Family
    Category
    Related To
  • What are the possible delay variations expected with the transmit and receive SERDES?
    989
    LatticeSC/M
    Architecture
    SERDES/PCS
  • What is the SERDES channel to channel transmit skew for the LatticeSC?
    985
    LatticeSC/M
    Architecture
    SERDES/PCS
  • The Lattice SC/M data sheet (DS1005) refers Fibre Channel users to the XAUI section of the data…
    982
    LatticeSC/M
    Architecture
    SERDES/PCS
  • What's the typical rise time for the LatticeSC SERDES reference clock(external CML input pin)?
    987
    LatticeSC/M
    Architecture
    SERDES/PCS
  • How do I interface an LVPECL clock source to a Lattice SERDES Reference Clocks (which is a CML…
    988
    All FPGA
    Architecture
    IO
  • GbE PCS:Why does the GbE PCS link state machine status signal regularly pulse low even though the…
    980
    All FPGA
    Architecture
    SERDES/PCS
  • Diamond: Timing: How do I define the skew of a registered bus to IOs?
    931
    All Devices
    Implementation
    Timing Analysis
  • Timing: What is the I/O Timing Report?
    938
    All Devices
    Implementation
    Timing Analysis
  • Diamond: Where can I find RTL coding examples?
    932
    All Devices
    Implementation
    Other
  • Lattice Diamond: How can I block clock transfers in the timing analysis tool?
    939
    All FPGA
    Implementation
    Timing Analysis
  • LatticeECP2/M/LatticeECP3: Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP…
    967
    All FPGA
    Lattice IP/Reference Design
    SGMII and Gb Ethernet PCS
  • How does the Ethernet flexiMAC deal with a Length/Type field that is smaller than Data payload size?…
    963
    LatticeSC/M
    Lattice MACO Cores
    Ethernet 1/10 Gigabit FlexiMAC
  • Does the LatticeSC/M Ethernet FlexiMAC IP report CRC errors on a frame after it removes data…
    969
    LatticeSC/M
    Lattice MACO Cores
    Ethernet 1/10 Gigabit FlexiMAC
  • SerDes: Do user need to regenerate the LatticeECP2M SERDES/PCSQUAD IPexpress model for different…
    968
    LatticeECP2/M
    Architecture
    SERDES/PCS
  • In the existing reference design for LatticeSC/M 10 GbE flexiMAC IP, can I simulate the core and…
    962
    LatticeSC/M
    Lattice MACO Cores
    Ethernet 1/10 Gigabit FlexiMAC
  • In IPUG48 (LatticeSCM Ethernet FLexiMAC USER GUIDE) what does the rb_flt_stt bus mean exactly?
    961
    LatticeSC/M
    Lattice MACO Cores
    Ethernet 1/10 Gigabit FlexiMAC
  • What happens to the existing packet whent the TX Etherne Fleximac underruns?
    966
    LatticeSC/M
    Lattice MACO Cores
    Ethernet 1/10 Gigabit FlexiMAC
  • Why is there a limit on the number of 5V tolerant IOs in the ispMACH 4000 devices?
    913
    All CPLD
    Architecture
    IO
  • How can I find out if the device I am currently using is still in production?
    916
    All Devices
    Reliability and Materials
    Lifetime
  • How to check Lattice device part number?
    919
    All Devices
    Inquiries
    Datasheet
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