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    ID
    Family
    Category
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  • Power Manager II: How many I2C loads can I put on an I2C chain for Power Manager II devices?
    280
    Power Manager II
    Customer Board Design
    Layout
  • DDR/DDR2/DDR3:  How do I implement differential SSTL pads in software for my DDR memory interface…
    297
    All FPGA
    Lattice IP/Reference Design
    DDR SDRAM Controller
  • Can I use an ispPAC-POWR6AT6 just to monitor voltages and not trim etc? If so, what is the simple…
    279
    Power Manager II
    Architecture
    Power
  • How do I build a SERDES External Link State Machine to perform word alignment?
    290
    All FPGA
    Architecture
    SERDES/PCS
  • Lattice Diamond: Is there a difference in size between an encrypted and unencrypted FPGA bitstream?…
    298
    All FPGA
    Device Programming
    Configuration/Programming
  • Can I buy factory-programmed Power Manager parts?
    278
    All Power Management
    Device Programming
    Customer Board
  • Lattice Diamond: Does the configuration file (such as an ECP3 bitstream) for SPI flash remain at…
    296
    LatticeECP3
    Device Programming
    ispVM System
  • Lattice Diamond: How do I generate a LatticeXP and LatticeXP2 device bit files for EPROM…
    295
    LatticeXP2
    Device Programming
    ispVM System
  • Lattice ispVM system: What can I do if the VME file size is larger than the non-volatile memory?
    293
    All FPGA
    Device Programming
    Embedded Programming
  • Power Manager II: Are there speed grades for different Power Manager II Devices, such as…
    271
    Power Manager II
    Inquiries
    Datasheet
  • PAC-Designer: How to implement multiple ispPAC-POWR1220AT8 Power Manager devices on a board?
    270
    All Power Management
    PAC-Designer
    LogiBuilder
  • PAC Designer: How to simulate a design with ProcessorPM-POWR605 device?
    273
    Power Manager II
    PAC-Designer
    Simulation
  • PAC-Designer: How do I change the Timers on a ProcessorPM-PM605?
    275
    Power Manager II
    PAC-Designer
    LogiBuilder
  • Where do I find pin function and placement information for my programmable device package?
    999
    All Devices
    Inquiries
    Datasheet
  • Are there any pins that can't be used when the SERDES is being used?
    990
    All FPGA
    Architecture
    IO
  • LatticeSC/M: How should I setup my SPI4.2 IP core power-on reset sequence?
    222
    LatticeSC/M
    Lattice IP/Reference Design
    SPI4.2
  • Are there any existing software tutorials and manuals for ispLEVER installation?
    227
    All CPLD
    Inquiries
    Tutorials
  • LatticeECP2/M: I need to connect an optical module to SERDES. Can you provide an example interface…
    998
    LatticeECP2/M
    Architecture
    SERDES/PCS
  • LatticeECP2/M: In external LSM mode, how does the word aligner hunt for comma during word…
    991
    LatticeECP2/M
    Architecture
    SERDES/PCS
  • LatticeMicoSystem: Why are there problems with my older LatticeMico32 System Builder after a newer…
    225
    All FPGA
    Implementation
    Mico32(MSB)
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