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    ID
    Family
    Category
    Related To
  • MACHXO2:  What's the difference between the TraceID and the USERCODE for MACHXO2 device?
    1424
    MachXO2
    Architecture
    Configuration/Programming
  • What is the function of the MachXO2 FPGA's Edge Clock Bridge?
    1426
    MachXO2
    Architecture
    PLL/DLL/Clock Routing
  • MachXO2: Can I configure the configuration SRAM memory with the Slave SPI Mode(SSPI)?
    1422
    MachXO2
    Architecture
    Configuration/Programming
  • MachXO2: How do I trigger the Dual Boot function?
    1421
    MachXO2
    Architecture
    Configuration/Programming
  • LatticeMicoSystem: What is the .ELF file that is generated by the LatticeMico32/LatticeMico8…
    1489
    All FPGA
    Implementation
    Mico32(MSB)
  • PAC-Designer: In PAC Designer software what does NODEx mean in Pin Definitions?
    1446
    All Power Management
    PAC-Designer
    LogiBuilder
  • LatticeMicoSystem: Upon starting LatticeMico8 compiler why do I receive error message "Cannot find…
    1441
    All Devices
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • LatticeMicoSystem: How do I generate LatticeMico8 executable ".mem" file?
    1443
    All Devices
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • PAC-Designer: Is there a I2C hardware verification utility available in the tool?
    1445
    All Mixed Signal
    PAC-Designer
    Design Utilities
  • LatticeMicoSystem: Are there any limitations to be aware of when using the LatticeMico8 C compiler?
    1442
    All Devices
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • Power Manager II: Can I program Hercules Demo Board using the USB cable provided with the kit?
    1449
    Power Manager II
    Lattice Evaluation Board
    Hercules-Standard
  • MachXO2:Q1. Are the Min and Max values mentioned in the MachXO2 datasheet DS1035 for oscillator are…
    3876
    MachXO2
    Inquiries
    Datasheet
  • PAC-Designer: How do PAC-Designer's project archiving functions work?
    1490
    All Mixed Signal
    PAC-Designer
    LogiBuilder
  • Lattice ispLever: How to specify where ispLEVER places a register through "synthesis LOC\u201D…
    1494
    All FPGA
    Implementation
    MAP
  • iCE40: What is the state of flip-flops during Power On Reset (POR) in iCE40 devices?
    3878
    iCE40
    Device Programming
    Configuration/Programming
  • Diamond 3.1: Why does the software shows compile issues when multidimensional arrays are packed?
    3879
    All FPGA
    Implementation
    Synthesis
  • Which HDL entry methods are available for Lattice Platform Manager devices?
    1496
    Platform Manager
    Entry
    Mixed Language
  • Power Manager II: Is there an "Boundary Scan Descriptive Language"  (BSDL) file available?  
    1495
    All Mixed Signal
    Device Modeling
    BSDL
  • Programmer: What is the maximum programming frequency achieved with HW-USBN-2A cable, while…
    3875
    MachXO2
    Device Programming
    Diamond Programmer
  • Synplify Pro: How do users prevent the Synplify synthesis tool from removing an unused input pin…
    1492
    All FPGA
    Implementation
    Synplicity
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