The CSM (Clock Synchronization Module) module of the DDR3 memory controller ipcore multiplies the input reference clock frequency four times for the DDR3 bus operations and two times for the local bus operations. This means that the DDR3 IP core uses 1:4:2 ratio (input clock vs. DDR3 clock vs. local clock). If you use a DDR3 IP core version 1.2 or later (or any DDR3 PHY IP core version), you can manually change this ratio by following the steps below:
1. Open the ddr3_pll.v file inside the models folder using a text editor. It is located under ddr_p_eval\models\ecp3.
2. Launch IPexpress and select "PLL". Configure the PLL with the options shown in the ddr3_pll.v file. Make sure you assign the module name to "ddr3_pll".
3. Change the input and output clock frequencies to your desired values. If you want to use 150MHz as DDR3 reference clock input and DDR3 memory clock is 300MHz, you can set CLKOP=300.0MHz CLKOK=150.0MHz. Click "Calculate" then "Generate".
4. If the generated PLL has more input or output pins than the original ddr_pll.v, you may need to manually edit the generated file so that the module can be properly instantiated. Use the original ddr3_pll.v file.
5. As an alternative, you can edit the original ddr_pll.v file with the divider values and parameters from the generated PLL module. You can select whichever way you feel more convenient.