Article Details

ID: 2041
Case Type: faq
Category: Lattice IP/Reference Design
Related To: DDR3 SDRAM Controller
Family: LatticeECP3

Search Answer Database

Search Text Image

How do I place DDR3 interface pins to minimize SSO impact?

1. Try using the DQS groups in the middle of the (right or left) edge if the DDR3 data width does not require to use the whole edge of LatticeECP3. Avoid the corner DQS groups if possible.

2. Locate a spacer DQS group between two adjacent data DQS groups if possible. A DQS group becomes a spacer DQS group if the I/O pads inside the group are not used as data pads (DQ, DQS, DM). The pads in a spacer group can be used for address, command, control or CK pads as well as for user logic or the pseudo power pads.

3. It is recommended that you locate four or more pseudo VCCIO/ground (GND) pads inside a spacer DQS group. An I/O pad becomes a pseudo power pad when it is configured to OUTPUT with its maximum driving strength (SSTL15, 10mA) and connected to the external VCCIO or ground power source on the PCB. Your design needs to drive the pseudo power I/O pads according to the external connection. (i.e., you assign them as OUTPUT and let your design drive "1" for pseudo VCCIO pads and "0" for pseudo GND pads in your RTL coding.) The recommended four pads are two pads in both ends (the first and the last ones in the group) and two DQS (positive and negative) pads in the middle.

4. You may have one remaining pad in a data DQS group which is not assigned as a data pad in a DDR3 interface. Assign it to pseudo VCCIO or pseudo GND. Preferred location is in the middle of the group (right beside DQS pads). Note that you will not have this extra pad if the DQS group includes a VREF1 pad for the bank.

5. Assign the DM (data mask) pad in a data DQS group close to the other side of DQS pads where a pseudo power pad is located. If the data DQS group includes VREF1, locate DM to the other side of VREF1 with respect to DQS. It can be used as an isolator due to its almost static nature in most applications.

6. Other DQS groups (neither data nor spacer group) can be used for accommodating DDR3 address, command, control and clock pads. It is recommended that you assign all or most DQS pads (positive and negative) in these groups to pseudo power. Since LatticeECP3 DQS pads have a dedicated DDR function that cannot be shared with other DDR3 signals, they are good pseudo power pad candidates.

7. You can assign all unused I/O pads to pseudo power if you do not have a plan to use them in the future. Assigning more I/O pads to VCCIO is desirable because LatticeECP3 has four VCCIO pads in each bank while more GND pads are available. Keep the total pseudo power pad ratio (VCCIO vs. GND) between 2:1 to 3:1.

8. Although it is not significantly necessary, it would be slightly more effective if you locate a pseudo VCCIO to a positive pad (A) and GND to a negative pad (B) of a PIO pair if possible.

9. If a bank includes unused input-only pads such as dedicated PLL input pads, connect them to VCCIO on your PCB. They can also be used as isolators and the connections on the board should provide good shielding. No extra consideration is necessary in your design.

10. It is a good idea to shield the VREF1 pad by locating pseudo power pads around it if the VREF1 pad is not located in a data DQS group.

11. Avoid fast switching signals being located close to the XRES pad. XRES requires an external resistor which is used to create the bias currents for the IO. Since this resistor is used for a calibration reference for sensitive on-chip circuitry, careful pin assignment around the XRES pad is also necessary to produce less jittery PLL outputs for DDR3 operations.

See TN1180 LatticeECP3 High-Speed I/O Interface, DDR3 Pinout Guidelines section for more general pinout guidelines along with these SSO guidelines.