MachXO

Versatile and non-volatile PLD for bridging, infinitely reconfigurable I/O expansion.

Related Products

Give Complexity the Boot – Designed to remove the complexity of choosing between CPLDs and low-capacity FPGAs – with glue logic, bus bridging, bus interfacing, power-up control, and control logic, you no longer need to choose.

Expand Your Interfaces – With up to 271 IOs, MachXO are perfect for a wide range of applications that require general purpose I/O expansion, interface bridging and power-up management functions.

To Infinite Reconfigurability and Beyond – Single chip solution featuring background programmable internal Flash memory and the ability for in-field logic updates during system configuration using TransFR™.

Features

  • Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM
  • SRAM based logic can be reconfigured in milliseconds using JTAG port
  • IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS
  • Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting
  • Available in TQFP, csBGA, caBGA and ftBGA packages

Jump to

Family Table

MachXO Device Selection Guide

Parameters LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
Density LUTs 256 256 640 640 1200 1200 2280 2280
EBR SRAM Blocks - - - - 1 1 3 3
EBR SRAM (Kbits) - - - - 9.2 9.2 27.6 27.6
Distributed RAM (Kbits) 2 2 6.1 6.1 6.4 6.4 7.7 7.7
PLL + DLL - - - - 1 + 0 1 + 0 2 + 0 2 + 0
Configuration Memory Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash
Dual Boot1 Yes Yes Yes Yes Yes Yes Yes Yes
Core Vcc 1.2 V Yes - Yes - Yes - Yes -
Core Vcc 1.8 - 3.3 V - Yes - Yes - Yes - Yes
Temp C Yes Yes Yes Yes Yes Yes Yes Yes
Temp I Yes Yes Yes Yes Yes Yes Yes Yes
Temp AEC-Q100 Yes Yes Yes Yes Yes - Yes -
0.5 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
100-ball csBGA (8 x 8 mm) 78 78 74 74
132-ball csBGA (8 x 8 mm) 101 101 101 101 101 101
100-pin TQFP (14 x 14 mm) 78 78 74 74 73 73 73 73
144-pin TQFP (20 x 20 mm) 113 113 113 113 113 113
0.8 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
256-ball caBGA (14 x 14 mm) 159 159 211 211 211 211
1.0 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
256-ball ftBGA (17 x 17 mm) 159 159 211 211 211 211
324-ball ftBGA (19 x 19 mm) 271 271

1. Dual Boot supported with external boot Flash.

Lattice Automotive (AEC-Q100 qualified) MachXO Device Selection Guide

Parameters LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
LUTs 256 647 1200 2280
Dist. RAM (Kbits) 2.0 6.0 6.25 7.5
EBR SRAM (Kbits) 0 0 9.2 27.6
Number of EBR SRAM Blocks (9 Kbits) 0 0 1 3
VCC Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2 1.2
NUmber of PLLs 0 0 1 2
Max. I/O 78 159 211 271
0.5 mm Spacing I/O Count
LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
100-pin Lead-Free TQFP (14 x 14 mm) 78 74 73 73
144-pin Lead-Free TQFP (20 x 20 mm) - 113 113 113
1.0 mm Spacing I/O Count
LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
256-ball Lead-Free ftBGA (17 x 17 mm) - 159 211 211
324-ball Lead-Free ftBGA (19 x 19 mm) - - - 271

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

To subscribe, or modify your subscription, to Document Notifications please login to your Lattice account

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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LA-MachXO Automotive Family Data Sheet
FPGA-DS-02070 1.6 1/22/2021 PDF 3 MB
MachXO Family Data Sheet
FPGA-DS-02071 3.3 7/30/2022 PDF 3.3 MB
MachXO Family Data Sheet (Japanese Language Version)
DS1002 02.8 6/1/2009 PDF 1.8 MB
Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
Linking or Selecting Ports with BSCAN2
FPGA-AN-02013 1.1 1/10/2022 PDF 680.9 KB
MachXO sysIO Usage Guide
TN1091 1.5 9/15/2010 PDF 425.4 KB
MachXO Density Migration
TN1097 1.0 9/1/2005 PDF 41.2 KB
Memory Usage Guide for MachXO Devices
TN1092 1.5 10/1/2010 PDF 1.4 MB
MachXO JTAG Programming and Configuration User Guide
FPGA-TN-02167 1.5 11/8/2022 PDF 906.6 KB
MachXO sysCLOCK Design and Usage Guide
TN1089 1.5 9/26/2011 PDF 1 MB
Input Hysteresis in Lattice CPLD and FPGA Devices
TN1112 1.1 9/1/2006 PDF 465.6 KB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-02016 1.1 6/21/2021 PDF 672.5 KB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-02312 1.1 6/23/2022 PDF 236.5 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.4 10/17/2023 PDF 1.4 MB
USB Programming and Circuit Guide
FPGA-AN-02015 1.2 1/22/2021 PDF 1.4 MB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-02017 1.1 1/9/2022 PDF 774.3 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.9 9/23/2024 PDF 878.5 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.4 8/27/2024 PDF 6.7 MB
Power Estimation and Management for MachXO Devices
TN1090 1.1 9/1/2007 PDF 1.9 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-02115 1.1 1/26/2022 PDF 708.9 KB
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077. 		AN8077 1.3 3/1/2015 PDF 2.4 MB
Thermal Management
FPGA-TN-02044 5.2 8/21/2024 PDF 756 KB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077 		AN8077 1.3 1/4/2013 RAR 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LA-MachXO Automotive Family Data Sheet
FPGA-DS-02070 1.6 1/22/2021 PDF 3 MB
MachXO Family Data Sheet
FPGA-DS-02071 3.3 7/30/2022 PDF 3.3 MB
MachXO Family Data Sheet (Japanese Language Version)
DS1002 02.8 6/1/2009 PDF 1.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-02081 1.1 8/27/2024 PDF 2.6 MB
Linking or Selecting Ports with BSCAN2
FPGA-AN-02013 1.1 1/10/2022 PDF 680.9 KB
MachXO sysIO Usage Guide
TN1091 1.5 9/15/2010 PDF 425.4 KB
MachXO Density Migration
TN1097 1.0 9/1/2005 PDF 41.2 KB
Memory Usage Guide for MachXO Devices
TN1092 1.5 10/1/2010 PDF 1.4 MB
MachXO JTAG Programming and Configuration User Guide
FPGA-TN-02167 1.5 11/8/2022 PDF 906.6 KB
MachXO sysCLOCK Design and Usage Guide
TN1089 1.5 9/26/2011 PDF 1 MB
Input Hysteresis in Lattice CPLD and FPGA Devices
TN1112 1.1 9/1/2006 PDF 465.6 KB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-02016 1.1 6/21/2021 PDF 672.5 KB
Wafer-Level Chip-Scale Package Guide
FPGA-TN-02312 1.1 6/23/2022 PDF 236.5 KB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.4 10/17/2023 PDF 1.4 MB
USB Programming and Circuit Guide
FPGA-AN-02015 1.2 1/22/2021 PDF 1.4 MB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-02017 1.1 1/9/2022 PDF 774.3 KB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.9 9/23/2024 PDF 878.5 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.4 8/27/2024 PDF 6.7 MB
Power Estimation and Management for MachXO Devices
TN1090 1.1 9/1/2007 PDF 1.9 MB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-02115 1.1 1/26/2022 PDF 708.9 KB
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077. 		AN8077 1.3 3/1/2015 PDF 2.4 MB
Thermal Management
FPGA-TN-02044 5.2 8/21/2024 PDF 756 KB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077 		AN8077 1.3 1/4/2013 RAR 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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POWR1014A Breakout Board Evaluation Kit User's Guide
EB64 01.1 2/13/2012 PDF 1.3 MB
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2 		IPUG18 9.2 11/8/2010 PDF 4.6 MB
MachXO 2280 Breakout Board Evaluation Kit User's Guide
FPGA-EB-02038 1.2 6/28/2021 PDF 2.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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WISHBONE UART - Source Code
RD1042 1.6 12/1/2014 ZIP 58.5 MB
Simple Sigma-Delta ADC, Documentation
FPGA-RD-02047 1.6 1/30/2020 PDF 971 KB
WISHBONE UART - Documentation
FPGA-RD-02137 1.7 2/5/2021 PDF 1.1 MB
SPI Flash Controller with Wear Leveling
FPGA-RD-02101 1.1 1/29/2021 PDF 1 MB
SPI WISHBONE Controller - Documentation
RD1044 1.7 3/1/2014 PDF 960 KB
Serial Peripheral Interface (SPI) - Documentation
RD1075 1.1 12/23/2011 PDF 158.7 KB
SMBus Controller Reference Design - Documentation
FPGA-RD-02100 1.1 1/22/2021 PDF 1.3 MB
SMBus Controller Reference Design Source Code
RD1098 1.0 11/8/2010 ZIP 2.2 MB
SPI Flash Controller with Wear Leveling - Source code
RD1102 1.0 11/8/2010 ZIP 952.2 KB
SD Flash Controller - Documentation
RD1048 1.1 1/29/2010 PDF 1.7 MB
SPI GPIO Expander - Documentation
RD1073 1.1 12/23/2010 PDF 212.5 KB
SD Flash Controller Using SD Bus - Documentation
RD1088 1.4 3/12/2014 PDF 1.4 MB
Simple Sigma-Delta ADC - Source Code
1.5 9/26/2018 ZIP 1.5 MB
WISHBONE-Compatible LCD Controller - Documentation
FPGA-RD-02102 1.3 1/29/2021 PDF 918.3 KB
WISHBONE-Compatible LCD Controller - Source Code
RD1053 1.2 11/8/2010 ZIP 140.9 KB
Single-Wire Controller for Digital Temp. Sensors Reference Design - Documentation
FPGA-RD-02099 1.1 1/22/2021 PDF 1.1 MB
SPI GPIO Expander - Source Code
RD1073 1.1 12/23/2010 ZIP 161.6 KB
SPI WISHBONE Controller - Source Code
RD1044 1.8 1/12/2015 ZIP 477.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD1075 1.1 12/23/2011 ZIP 124.8 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
RD1011 1.7 1/1/2015 ZIP 766.4 KB
Wake on LAN - Source Code
RD1096 1.0 6/24/2010 ZIP 283.1 KB
Single-Wire Controller for Digital Temp Sensors Reference Design - Source Code
RD1099 1.0 11/8/2010 ZIP 513.1 KB
SD Flash Controller Using SD Bus - Source Code
RD1088 1.4 3/12/2014 ZIP 5 MB
Wake on LAN - Documentation
RD1096 1.0 6/24/2010 PDF 311.6 KB
I2S Controller with WISHBONE Interface Reference Design - Source Code
RD1101 1.1 3/1/2014 ZIP 1.6 MB
IDE/ATA Interface Controller - WISHBONE Compatible - Source Code
RD1095 1.0 6/28/2010 ZIP 756.3 KB
IDE/ATA Interface Controller - WISHBONE Compatible - Documentation
RD1095 1.0 6/28/2010 PDF 769.8 KB
HDLC Controller for FPGAs - Documentation
RD1038 01.1 9/4/2008 PDF 1.1 MB
GPIO Expander, Documentation
RD1065 1.3 4/12/2011 PDF 280.6 KB
GPIO Expander, Source Code
RD1065 1.3 4/12/2011 ZIP 195.5 KB
Fast Page Mode SDRAM Controller - Documentation
FPGA-RD-02090 2.4 1/22/2021 PDF 887.1 KB
I2C Slave to SPI Master Bridge - Documentation
FPGA-RD-02111 1.2 1/29/2021 PDF 863.9 KB
Fast Page Mode SDRAM Controller - Source Code
RD1014 2.3 11/8/2010 ZIP 110.4 KB
I2C Master with WISHBONE Bus Interface - Source Code
RD1046 1.8 2/1/2016 ZIP 1.4 MB
I2C Controller for Serial EEPROMs - Documentation
RD1006 2.6 3/5/2014 PDF 767.9 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD1005 5.9 1/10/2015 ZIP 809.7 KB
I2C Controller for Serial EEPROMs - Source Code
RD1006 2.7 1/12/2015 ZIP 613.5 KB
I2C Master with WISHBONE Bus Interface - Documentation
RD1046 1.6 1/15/2015 PDF 1.4 MB
HDLC Controller for FPGAs - Source Code
RD1038 1.0 9/4/2008 ZIP 1.2 MB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD1005 5.8 3/6/2014 PDF 987.4 KB
I2S Controller with WISHBONE Interface Reference Design Documentation
RD1101 1.1 3/1/2014 PDF 2.4 MB
I2C Slave to SPI Master Bridge - Source Code
RD1094 1.1 12/23/2011 ZIP 180.4 KB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-02106 4.9 1/29/2021 PDF 918.1 KB
Advanced SDR SDRAM Controller - Design Documentation
FPGA-RD-02087 4.9 1/22/2021 PDF 1.1 MB
Delta Sigma ADC - Documentation
RD1063 1.0 10/19/2009 PDF 110.9 KB
8b/10b Encoder/Decoder - Source Code
1.4 1/29/2021 ZIP 1.9 MB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD1001 7.3 4/18/2011 ZIP 152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD1002 4.6 3/13/2014 ZIP 2.6 MB
CompactFlash Controller - Documentation
FPGA-RD-02088 1.4 1/22/2021 PDF 1.7 MB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-02105 7.4 1/29/2021 PDF 993.7 KB
Arbitration and Switching Between Bus Masters - Documentation
FPGA-RD-02104 1.2 1/21/2021 PDF 952.5 KB
Advanced SDR SDRAM Controller - Source Code
RD1010 4.8 9/12/2014 ZIP 495.7 KB
8b/10b Encoder/Decoder - Documentation
FPGA-RD-02103 1.5 1/29/2021 PDF 940.3 KB
Control Link Serial Interface - Documentation
FPGA-RD-02089 1.5 1/22/2021 PDF 810.2 KB
CompactFlash Controller - Source Code
RD1040 1.4 11/8/2010 ZIP 1.5 MB
Control Link Serial Interface - Source Code
RD1051 1.4 11/8/2010 ZIP 240.7 KB
Arbitration and Switching Between Bus Masters - Source code
RD1067 1.1 2/22/2010 ZIP 284 KB
Power Supply Fault Logging - Source Code
RD1062 1.2 6/30/2010 ZIP 123.4 KB
PWM Fan Controller - Source Code
RD1060 1.7 1/16/2015 ZIP 2.9 MB
RD1026 LatticeMico8 Microcontroller User's Guide
2.1 11/8/2014 PDF 2.1 MB
NOR Flash Memory Controller with WISHBONE Interface - Documentation
FPGA-RD-02096 1.2 1/22/2021 PDF 1.6 MB
Power Management Bus Reference Design Documentation
FPGA-RD-02097 1.2 1/22/2021 PDF 1.1 MB
Read and Write Usercode - Source Code
RD1041 1.3 3/1/2014 ZIP 618.2 KB
NAND Flash Controller Design - Documentation
FPGA-RD-02095 1.3 1/22/2021 PDF 1.6 MB
Power Supply Fault Logging - Documentation
RD1062 1.2 6/30/2010 PDF 127.8 KB
PCI to NOR Flash Interface - Source Code
RD1050 1.1 3/10/2010 ZIP 3.8 MB
PCI Target 32-bit/33MHz
FPGA-RD-02134 3.6 1/31/2021 PDF 1.8 MB
PCI Target (33MHz, 32 Bit ) - Source Code
RD1008 3.5 8/20/2013 ZIP 980.4 KB
Power Management Bus Reference Design - Source Code
RD1100 1.1 12/23/2011 ZIP 378.3 KB
NAND Flash Controller - Source Code
RD1055 1.4 11/8/2014 ZIP 912.7 KB
NOR Flash Memory Controller with WISHBONE Interface - Source Code
RD1087 1.1 11/8/2010 ZIP 198.1 KB
PCI/WISHBONE Bridge - Source Code
RD1045 1.3 4/10/2011 ZIP 4.5 MB
PCI to NOR Flash Interface
RD1050 1.1 3/10/2010 PDF 367.9 KB
PCI/WISHBONE Bridge
FPGA-RD-02135 1.4 2/5/2021 PDF 1.2 MB
Read and Write Usercode - Documentation
RD1041 1.4 9/17/2014 PDF 831.5 KB
PWM Fan Controller
RD1060 1.6 9/10/2014 PDF 481.5 KB
MachXO 2280 Breakout Board Evaluation Kit Source Code
This demo includes the Lattice Diamond project source for the preprogrammed demonstration design. It programs the LCMXO2280-FTN256 with a counter circuit using the embedded oscillator timer and sysIO Buffers configured for LED drive 		1.0 3/21/2011 ZIP 10.7 KB
LatticeMico8 v3.0 Verilog
3.0 2/19/2008 ZIP 1.1 MB
MDIO Peripheral - WISHBONE Compatible - Source Code
RD1074 1.1 2/19/2010 ZIP 354.1 KB
MDIO (Management Data Input/Output Interface) Peripheral - WISHBONE Compatible
FPGA-RD-02130 1.2 1/31/2021 PDF 1021 KB
LatticeMico8 to WISHBONE Interface Adapter - Documentation
RD1043 1.1 2/23/2010 PDF 126.2 KB
LED/OLED Driver - Source code
RD1103 1.1 3/1/2014 ZIP 1.4 MB
LPC (Low Pin Count) Bus Controller - Source Code
RD1049 1.6 4/12/2011 ZIP 517.2 KB
LPC (Low Pin Count) Bus Controller Reference Design - Documentation
FPGA-RD-02114 1.7 1/21/2021 PDF 1 MB
LatticeMico8 to WISHBONE Interface Adapter - Source Code
RD1043 1.1 2/23/2010 ZIP 109.3 KB
LED/OLED Driver - Documentation
RD1103 1.1 3/1/2014 PDF 989.6 KB
LatticeMico8 v3.1 Verilog
RD1026 3.1 4/9/2010 ZIP 913.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MachXO 300 mm Fab Transition Circuit Observations Mitigation
PB1377 2.0 6/12/2017 PDF 82.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PCN14A-09 Notification of Intent to Utilize AQAS and AQMS for MachXO 324-ftBGA Devices
PCN14A-09 1 8/1/2009 PDF 41.8 KB
PCN14A-09 MachXO2280 324-ftBGA ASEM AQAS AQMS - Japanese Language
PCN14A-09 1 8/1/2009 PDF 132.1 KB
PCN 02A-15 Affected_OPN_Listing
Discontinuance 		3.0 8/12/2015 XLSX 310.4 KB
PCN 02A-15 SnPb and Select Mature Family Discontinuance
1.0 6/18/2015 PDF 316.9 KB
PCN02A-15 Frequently Asked Questions
2.0 6/18/2015 DOCX 60.8 KB
PCN05A-17 Halogen-Free substrate at ASEM
1.2 10/27/2017 PDF 268 KB
PCN05A-17 Affected Parts List
1.0 1/1/0001 XLSX 14.9 KB
PCN 09A-12 Affected Devices
Assembly Site 		PCN09A-12 1.0 5/14/2012 XLSX 121 KB
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-12 1.0 5/14/2012 PDF 160.2 KB
PCN 09A-12 Material Set Changes
Assembly Site 		PCN09A-12 1.0 5/14/2012 XLSX 121 KB
PCN 09A-12 Frequently Asked Questions
PCN09A-12 1.0 5/11/2012 PDF 178.9 KB
PCN03A-13 Device Characterization Report
PCN03A-13 6/28/2013 PDF 981.3 KB
PCN 03B13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set 		PCN03B 1.0 11/14/2014 PDF 229.6 KB
PCN03A-13 FAQs
PCN03A-13 6/28/2013 PDF 458.3 KB
PCN03B-13 Affected Part Number and Material Sets
PCN03B-13 6/28/2013 XLSX 69 KB
ACN 05A-13 XO Transfer
Mask Set 		ACN05A-13 7/11/2013 PDF 118.7 KB
PCN08A13_AffectedDevices
Other 		PCN08A-13 1 9/26/2013 XLSX 78.2 KB
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-13 6/28/2013 PDF 202.5 KB
PCN07A-14 LA-MachXO Product Family AEC-Q100 Qualification Summary
PCN07A-14 1.0 12/18/2014 PDF 638.8 KB
PCN03A-14 Characterization Report
PCN03A-14 1.0 4/4/2014 PDF 919.5 KB
PCN05A-14 Notification of Intent to Utilize an Alternate Qualified Foundry and Alternate Qualified Mask Sets for the MachXO Products
Foundry, Mask Set 		PCN05A-14 1.1 2/5/2016 PDF 152.8 KB
PCN06A-14 Affected Device List
PCN06A-14 1.0 10/3/2014 XLSX 45.1 KB
PCN05A-14 Characterization Report
PCN05A-14 1.0 6/6/2014 PDF 499.2 KB
PCN05A-14 Affected Part Number List
PCN05A-14 1.0 6/6/2014 XLSX 18.6 KB
PCN06A-14 Material Set Table
PCN06A-14 1.0 10/3/2014 XLSX 13.7 KB
PCN06A-14 Characterization Report
PCN06A-14 1.0 10/3/2014 PDF 563.7 KB
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-14 1.0 11/21/2014 PDF 229.5 KB
PCN07A-14 FAQ
Foundry, Mask Set 		PCN07A-14 1.0 12/18/2014 PDF 89.6 KB
PCN03A-14 FAQ
PCN03A-14 1.0 4/4/2014 PDF 452.5 KB
PCN03A-14 Material Set Table
PCN03A-14 1.0 4/4/2014 XLSX 26.9 KB
PCN05A-14 FAQ
PCN05A-14 1.0 6/6/2014 PDF 193.9 KB
PCN03A-14 Affected Part Number List
PCN03A-14 1.0 4/4/2014 XLSX 60 KB
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-14 1.0 11/21/2014 PDF 229.9 KB
PCN07A-14 Automotive XO foundry transfer
PCN07A-14 1.0 12/18/2014 PDF 430.8 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set 		PCN06C-11 1.0 8/1/2011 PDF 838.5 KB
ACN03D-11 Withdrawal of ACN03C-11
Material Set 		ANC03D-11 1 4/1/2011 PDF 796.6 KB
PCN07C-11 Withdrawal of PCN07B-11
Material Set 		PCN07C-11 1.0 8/1/2011 PDF 917.9 KB
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.2 8/8/2024 ZIP 2.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Product Selector Guide
I0211 46.0 7/18/2024 PDF 9.7 MB
MachXO Product Brief
I0176 7.0 1/14/2013 PDF 1.3 MB
MachXO Product Brief (Chinese)
I0176C 8.0 1/14/2013 PDF 1.3 MB
MachXO Control Development Kit Brochure
I0206 1.0 10/19/2009 PDF 1007.2 KB
MachXO Mini Development Kit Product Brief
I0199 1.0 2/23/2009 PDF 815.3 KB
MachXO Product Brief (Japanese)
I0176J 7.0 4/2/2010 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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FTN256_LAXP2_LAMXO
Rev H1 6/9/2022 PDF 141.3 KB
FTN324_LAMXO
Rev F1 6/9/2022 PDF 140.9 KB
TN100_LAMXO
Rev B 4/19/2018 PDF 22 KB
TN144_LA
Rev C 4/25/2018 PDF 22.1 KB
TN_TG_TQ144 Cu_wire all
Rev E1 12/21/2021 PDF 107.1 KB
FTN324
Rev P1 6/9/2022 PDF 153.4 KB
MN100_XO
Rev Q1 6/21/2022 PDF 152.9 KB
TN_TG100 Cu_wire all
Rev D2 12/21/2021 PDF 25.4 KB
MN132_Cu_all
Rev R1 6/21/2022 PDF 149.6 KB
FTN256_v1_Cu_XO_XP2
Rev. R1 6/9/2022 PDF 150.2 KB
BN256_XO
Rev R1 6/9/2022 PDF 151.4 KB
Lattice MachXO Product Family Qualification Summary
Deleted last three pages 		H 1/23/2015 PDF 654.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Creating An ADC Using FPGA Resources
1.0 3/1/2010 PDF 272.2 KB
Expanding Microprocessor Connectivity Using Low-cost FPGAs
1.0 8/28/2013 PDF 474.4 KB
Dual Sensor Design Solution - White Paper (Chinese Language Version)
1.0 5/31/2012 PDF 236.6 KB
Pre-tested Design Accelerates Development (Korean Language)
1.0 3/1/2010 PDF 1.4 MB
Pre-tested Design Accelerates Development (Chinese Language)
1.0 6/28/2010 PDF 1.1 MB
Pre-tested Design Accelerates Development
1.0 3/1/2010 PDF 299.3 KB
Pre-tested Design Accelerates Development (Traditional Chinese Language)
1.0 6/28/2010 PDF 1.2 MB
The Challenges of Automotive Vision Systems Design
4/1/2007 PDF 341.5 KB
MachXO: Platform Management Using Low-Cost Non-Volatile PLDs
2/23/2009 PDF 512.9 KB
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages (Chinese Language)
1.0 7/1/2010 PDF 488.5 KB
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages
1.0 7/1/2010 PDF 443.6 KB
MachXO PLDs in System Control Designs
1.0 10/19/2009 PDF 876.7 KB
MachXO: Platform Management Using Low-Cost Non-Volatile PLDs (Chinese Language)
1.0 6/8/2009 PDF 389.2 KB
ispMACH 4000ZE Practical Low Power CPLD Design
8/25/2009 PDF 136.5 KB
MachXO: Optimized Programmable Devices for Bus Interfaces, Bridges and Control
7/1/2005 PDF 126.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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[BSDL] LCMXO2280C caBGA 256
1.00 6/29/2009 BSM 48.1 KB
[BSDL] LCMXO640E csBGA 100
1.04 4/16/2008 BSM 28 KB
[BSDL] LCMXO640E TQFP 144
1.04 4/16/2008 BSM 31.5 KB
[BSDL] LCMXO640E csBGA 132
1.04 4/16/2008 BSM 30.5 KB
[BSDL] LCMXO2280C ftBGA 324
1.03 4/16/2008 BSM 54.2 KB
[BSDL] LCMXO2280C TQFP 100
1.03 4/16/2008 BSM 36.5 KB
[BSDL] LCMXO640C TQFP 144
1.04 4/16/2008 BSM 32.1 KB
[BSDL] LCMXO2280E TQFP 100
1.03 4/16/2008 BSM 35.8 KB
[BSDL] LCMXO1200C TQFP 100
1.02 4/16/2008 BSM 32.1 KB
[BSDL] LCMXO1200E TQFP 144
1.03 4/16/2008 BSM 35.3 KB
[BSDL] LCMXO2280C ftBGA 256
1.03 4/16/2008 BSM 48.8 KB