MachXO – Interface Bridging

Versatile and non-volatile PLD for bridging, infinitely reconfigurable I/O expansion.

Related Products


MachXO3

Give Complexity the Boot – Designed to remove the complexity of choosing between CPLDs and low-capacity FPGAs – with glue logic, bus bridging, bus interfacing, power-up control, and control logic, you no longer need to choose.

Expand Your Interfaces – With up to 271 IOs, MachXO are perfect for a wide range of applications that require general purpose I/O expansion, interface bridging and power-up management functions.

To Infinite Reconfigurability and Beyond – Single chip solution featuring background programmable internal Flash memory and the ability for in-field logic updates during system configuration using TransFR™.

Features

  • Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM
  • SRAM based logic can be reconfigured in milliseconds using JTAG port
  • IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS
  • Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting
  • Available in TQFP, csBGA, caBGA and ftBGA packages

Jump to

Family Table

MachXO Device Selection Guide

Parameters LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
Density LUTs 256 256 640 640 1200 1200 2280 2280
EBR SRAM Blocks - - - - 1 1 3 3
EBR SRAM (Kbits) - - - - 9.2 9.2 27.6 27.6
Distributed RAM (Kbits) 2 2 6.1 6.1 6.4 6.4 7.7 7.7
PLL + DLL - - - - 1 + 0 1 + 0 2 + 0 2 + 0
Configuration Memory Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash
Dual Boot1 Yes Yes Yes Yes Yes Yes Yes Yes
Core Vcc 1.2 V Yes - Yes - Yes - Yes -
Core Vcc 1.8 - 3.3 V - Yes - Yes - Yes - Yes
Temp C Yes Yes Yes Yes Yes Yes Yes Yes
Temp I Yes Yes Yes Yes Yes Yes Yes Yes
Temp AEC-Q100 Yes Yes Yes Yes Yes - Yes -
0.5 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
100-ball csBGA (8 x 8 mm) 78 78 74 74
132-ball csBGA (8 x 8 mm) 101 101 101 101 101 101
100-pin TQFP (14 x 14 mm) 78 78 74 74 73 73 73 73
144-pin TQFP (20 x 20 mm) 113 113 113 113 113 113
0.8 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
256-ball caBGA (14 x 14 mm) 159 159 211 211 211 211
1.0 mm Spacing I/O Count
  LCMXO256E LCMXO256C LCMXO640E LCMXO640C LCMXO1200E LCMXO1200C LCMXO2280E LCMXO2280C
256-ball ftBGA (17 x 17 mm) 159 159 211 211 211 211
324-ball ftBGA (19 x 19 mm) 271 271

1. Dual Boot supported with external boot Flash.

Lattice Automotive (AEC-Q100 qualified) MachXO Device Selection Guide

Parameters LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
LUTs 256 647 1200 2280
Dist. RAM (Kbits) 2.0 6.0 6.25 7.5
EBR SRAM (Kbits) 0 0 9.2 27.6
Number of EBR SRAM Blocks (9 Kbits) 0 0 1 3
VCC Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2 1.2
NUmber of PLLs 0 0 1 2
Max. I/O 78 159 211 271
0.5 mm Spacing I/O Count
LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
100-pin Lead-Free TQFP (14 x 14 mm) 78 74 73 73
144-pin Lead-Free TQFP (20 x 20 mm) - 113 113 113
1.0 mm Spacing I/O Count
LAMXO256E/C LAMXO640E/C LAMXO1200E LAMXO2280E
256-ball Lead-Free ftBGA (17 x 17 mm) - 159 211 211
324-ball Lead-Free ftBGA (19 x 19 mm) - - - 271

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

To subscribe, or modify your subscription, to Document Notifications please login to your Lattice account

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
LA-MachXO Automotive Family Data Sheet
DS1003 1.5 11/20/2007
MachXO Family Data Sheet
DS1002 3.1 6/21/2017
MachXO Family Data Sheet (Japanese Language Version)
DS1002 02.8 6/1/2009
Linking or Selecting Ports with BSCAN2
AN8083 1.0 10/19/2009
MachXO sysIO Usage Guide
TN1091 1.5 9/15/2010
MachXO Density Migration
TN1097 1.0 9/1/2005
Memory Usage Guide for MachXO Devices
TN1092 1.5 10/1/2010
MachXO JTAG Programming and Configuration User's Guide
TN1086 1.4 6/1/2010
MachXO sysCLOCK Design and Usage Guide
TN1089 1.5 9/26/2011
Input Hysteresis in Lattice CPLD and FPGA Devices
TN1112 1.1 9/1/2006
Using a Discrete Crystal as a PLD Clock Source
AN8080 01.0 6/15/2009
Minimizing System Interruption During Configuration Using TransFR Technology
TN1087 3.7 10/30/2015
Wafer-Level Chip-Scale Package Guide
TN1242 1.0 7/13/2011
USB Programming and Circuit Guide
AN8082 01.1 1/13/2011
Using Multiple Boundary Scan Port Linker (BSCAN2)
AN8081 01.0 7/1/2009
Power Estimation and Management for MachXO Devices
TN1090 1.1 9/1/2007
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077. 		AN8077 1.3 3/1/2015
Thermal Management
FPGA-TN-02044 3.5 12/10/2019
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077 		AN8077 1.3 1/4/2013
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.0 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LA-MachXO Automotive Family Data Sheet
DS1003 1.5 11/20/2007
MachXO Family Data Sheet
DS1002 3.1 6/21/2017
MachXO Family Data Sheet (Japanese Language Version)
DS1002 02.8 6/1/2009
TITLE NUMBER VERSION DATE FORMAT SIZE
Linking or Selecting Ports with BSCAN2
AN8083 1.0 10/19/2009
MachXO sysIO Usage Guide
TN1091 1.5 9/15/2010
MachXO Density Migration
TN1097 1.0 9/1/2005
Memory Usage Guide for MachXO Devices
TN1092 1.5 10/1/2010
MachXO JTAG Programming and Configuration User's Guide
TN1086 1.4 6/1/2010
MachXO sysCLOCK Design and Usage Guide
TN1089 1.5 9/26/2011
Input Hysteresis in Lattice CPLD and FPGA Devices
TN1112 1.1 9/1/2006
Using a Discrete Crystal as a PLD Clock Source
AN8080 01.0 6/15/2009
Minimizing System Interruption During Configuration Using TransFR Technology
TN1087 3.7 10/30/2015
Wafer-Level Chip-Scale Package Guide
TN1242 1.0 7/13/2011
USB Programming and Circuit Guide
AN8082 01.1 1/13/2011
Using Multiple Boundary Scan Port Linker (BSCAN2)
AN8081 01.0 7/1/2009
Power Estimation and Management for MachXO Devices
TN1090 1.1 9/1/2007
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077. 		AN8077 1.3 3/1/2015
Thermal Management
FPGA-TN-02044 3.5 12/10/2019
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077 		AN8077 1.3 1/4/2013
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.0 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO 2280 Breakout Board Evaluation Kit User's Guide
EB66 1.1 2/21/2015
POWR1014A Breakout Board Evaluation Kit User's Guide
EB64 01.1 2/13/2012
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2 		IPUG18 9.2 11/8/2010
TITLE NUMBER VERSION DATE FORMAT SIZE
WISHBONE UART - Source Code
RD1042 1.6 12/1/2014 ZIP 58.5 MB
SPI WISHBONE Controller - Documentation
RD1044 1.7 3/1/2014
Serial Peripheral Interface (SPI) - Documentation
RD1075 1.1 12/23/2011
SMBus Controller Reference Design Documentation
RD1098 1.0 11/8/2010
SMBus Controller Reference Design Source Code
RD1098 1.0 11/8/2010
SPI Flash Controller with Wear Leveling - Source code
RD1102 1.0 11/8/2010
SD Flash Controller - Documentation
RD1048 1.1 1/29/2010
SPI GPIO Expander - Documentation
RD1073 1.1 12/23/2010
SD Flash Controller Using SD Bus - Documentation
RD1088 1.4 3/12/2014
Simple Sigma-Delta ADC - Source Code
1.5 9/26/2018
WISHBONE-Compatible LCD Controller - Documentation
RD1053 1.2 11/8/2010
WISHBONE-Compatible LCD Controller - Source Code
RD1053 1.2 11/8/2010
Single-Wire Controller for Digital Temp. Sensors Reference Design Documentation
RD1099 1.0 11/8/2010
SPI GPIO Expander - Source Code
RD1073 1.1 12/23/2010
SPI WISHBONE Controller - Source Code
RD1044 1.8 1/12/2015
Serial Peripheral Interface (SPI) - Source Code
RD1075 1.1 12/23/2011
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
RD1011 1.7 1/1/2015
Wake on LAN - Source Code
RD1096 1.0 6/24/2010
Single-Wire Controller for Digital Temp Sensors Reference Design - Source Code
RD1099 1.0 11/8/2010
SD Flash Controller Using SD Bus - Source Code
RD1088 1.4 3/12/2014
Wake on LAN - Documentation
RD1096 1.0 6/24/2010
I2S Controller with WISHBONE Interface Reference Design - Source Code
RD1101 1.1 3/1/2014
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD1054 1.6 12/1/2014
IDE/ATA Interface Controller - WISHBONE Compatible - Source Code
RD1095 1.0 6/28/2010
IDE/ATA Interface Controller - WISHBONE Compatible - Documentation
RD1095 1.0 6/28/2010
HDLC Controller for FPGAs - Documentation
RD1038 01.1 9/4/2008
GPIO Expander, Documentation
RD1065 1.3 4/12/2011
GPIO Expander, Source Code
RD1065 1.3 4/12/2011
Fast Page Mode SDRAM Controller - Documentation
Also download the source code below 		RD1014 2.3 11/8/2010
I2C Slave to SPI Master Bridge - Documentation
RD1094 1.1 12/23/2011
Fast Page Mode SDRAM Controller - Source Code
RD1014 2.3 11/8/2010
I2C Master with WISHBONE Bus Interface - Source Code
RD1046 1.8 2/1/2016
I2C Controller for Serial EEPROMs - Documentation
RD1006 2.6 3/5/2014
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD1005 5.9 1/10/2015
I2C Controller for Serial EEPROMs - Source Code
RD1006 2.7 1/12/2015
I2C Master with WISHBONE Bus Interface - Documentation
RD1046 1.6 1/15/2015
HDLC Controller for FPGAs - Source Code
RD1038 1.0 9/4/2008
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD1005 5.8 3/6/2014
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD1054 1.6 12/12/2014
I2S Controller with WISHBONE Interface Reference Design Documentation
RD1101 1.1 3/1/2014
I2C Slave to SPI Master Bridge - Source Code
RD1094 1.1 12/23/2011
BSCAN2 - Multiple Scan Port Linker - Documentation
RD1002 4.8 1/30/2017
Advanced SDR SDRAM Controller - Design Documentation
RD1010 4.8 8/20/2014
Delta Sigma ADC - Documentation
RD1063 1.0 10/19/2009
8b/10b Encoder/Decoder - Source Code
RD1012 1.2 4/12/2011
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD1001 7.3 4/18/2011
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD1002 4.6 3/13/2014
CompactFlash Controller - Documentation
RD1040 1.3 11/8/2010
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
RD1001 7.3 4/18/2011
Arbitration and Switching Between Bus Masters - Documentation
RD1067 1.1 2/22/2010
Advanced SDR SDRAM Controller - Source Code
RD1010 4.8 9/12/2014
8b/10b Encoder/Decoder - Documentation
Also download the source code below 		RD1012 1.4 1/13/2015
Control Link Serial Interface - Documentation
RD1051 1.4 11/8/2010
CompactFlash Controller - Source Code
RD1040 1.4 11/8/2010
Control Link Serial Interface - Source Code
RD1051 1.4 11/8/2010
Arbitration and Switching Between Bus Masters - Source code
RD1067 1.1 2/22/2010
LatticeMico8 v3.0 Verilog
3.0 2/19/2008
MDIO Peripheral - WISHBONE Compatible - Source Code
RD1074 1.1 2/19/2010
MDIO (Management Data Input/Output Interface) Peripheral - WISHBONE Compatible
RD1074 1.1 4/1/2011
LatticeMico8 to WISHBONE Interface Adapter - Documentation
RD1043 1.1 2/23/2010
LED/OLED Driver - Source code
RD1103 1.1 3/1/2014
LPC (Low Pin Count) Bus Controller - Source Code
RD1049 1.6 4/12/2011
LPC (Low Pin Count) Bus Controller Reference Design - Documentation
RD1049 1.6 4/12/2011
LatticeMico8 to WISHBONE Interface Adapter - Source Code
RD1043 1.1 2/23/2010
LED/OLED Driver - Documentation
RD1103 1.1 3/1/2014
LatticeMico8 v3.1 Verilog
RD1026 3.1 4/9/2010
MachXO 2280 Breakout Board Evaluation Kit Source Code
This demo includes the Lattice Diamond project source for the preprogrammed demonstration design. It programs the LCMXO2280-FTN256 with a counter circuit using the embedded oscillator timer and sysIO Buffers configured for LED drive 		1.0 3/21/2011
Power Supply Fault Logging - Source Code
RD1062 1.2 6/30/2010
PWM Fan Controller - Source Code
RD1060 1.7 1/16/2015
RD1026 LatticeMico8 Microcontroller User's Guide
2.1 11/8/2014
NOR Flash Memory Controller with WISHBONE Interface - Documentation
RD1087 1.1 11/8/2010
Power Management Bus Reference Design Documentation
RD1100 1.1 12/23/2011
Read and Write Usercode - Source Code
RD1041 1.3 3/1/2014
NAND Flash Controller Design - Documentation
RD1055 1.2 11/1/2010
Power Supply Fault Logging - Documentation
RD1062 1.2 6/30/2010
PCI to NOR Flash Interface - Source Code
RD1050 1.1 3/10/2010
PCI Target 32-bit/33MHz
RD1008 3.5 8/19/2013
PCI Target (33MHz, 32 Bit ) - Source Code
RD1008 3.5 8/20/2013
Power Management Bus Reference Design - Source Code
RD1100 1.1 12/23/2011
NAND Flash Controller - Source Code
RD1055 1.4 11/8/2014
NOR Flash Memory Controller with WISHBONE Interface - Source Code
RD1087 1.1 11/8/2010
PCI/WISHBONE Bridge - Source Code
RD1045 1.3 4/10/2011
PCI to NOR Flash Interface
RD1050 1.1 3/10/2010
PCI/WISHBONE Bridge
RD1045 1.3 4/10/2011
Read and Write Usercode - Documentation
RD1041 1.4 9/17/2014
PWM Fan Controller
RD1060 1.6 9/10/2014
Simple Sigma-Delta ADC, Documentation
FPGA-RD-02047 1.5 9/26/2018
WISHBONE UART - Documentation
RD1042 1.6 12/1/2014
SPI Flash Controller with Wear Leveling
RD1102 1.0 11/8/2010
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO 300 mm Fab Transition Circuit Observations Mitigation
PB1377 2.0 6/12/2017
TITLE NUMBER VERSION DATE FORMAT SIZE
PCN 09A-12 Affected Devices
Assembly Site 		PCN09A-12 1.0 5/14/2012
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-12 1.0 5/14/2012
PCN 09A-12 Material Set Changes
Assembly Site 		PCN09A-12 1.0 5/14/2012
PCN 09A-12 Frequently Asked Questions
PCN09A-12 1.0 5/11/2012
PCN06C-11 Withdrawal of PCN06B-11
Material Set 		PCN06C-11 1.0 8/1/2011
ACN03D-11 Withdrawal of ACN03C-11
Material Set 		ANC03D-11 1 4/1/2011
PCN07C-11 Withdrawal of PCN07B-11
Material Set 		PCN07C-11 1.0 8/1/2011
PCN03A-13 Device Characterization Report
PCN03A-13 6/28/2013
PCN 03B13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set 		PCN03B 1.0 11/14/2014
PCN03A-13 FAQs
PCN03A-13 6/28/2013
PCN03B-13 Affected Part Number and Material Sets
PCN03B-13 6/28/2013
ACN 05A-13 XO Transfer
Mask Set 		ACN05A-13 7/11/2013
PCN08A13_AffectedDevices
Other 		PCN08A-13 1 9/26/2013
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-13 6/28/2013
PCN07A-14 LA-MachXO Product Family AEC-Q100 Qualification Summary
PCN07A-14 1.0 12/18/2014
PCN03A-14 Characterization Report
PCN03A-14 1.0 4/4/2014
PCN05A-14 Notification of Intent to Utilize an Alternate Qualified Foundry and Alternate Qualified Mask Sets for the MachXO Products
Foundry, Mask Set 		PCN05A-14 1.1 2/5/2016
PCN06A-14 Affected Device List
PCN06A-14 1.0 10/3/2014
PCN05A-14 Characterization Report
PCN05A-14 1.0 6/6/2014
PCN05A-14 Affected Part Number List
PCN05A-14 1.0 6/6/2014
PCN06A-14 Material Set Table
PCN06A-14 1.0 10/3/2014
PCN06A-14 Characterization Report
PCN06A-14 1.0 10/3/2014
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-14 1.0 11/21/2014
PCN07A-14 FAQ
Foundry, Mask Set 		PCN07A-14 1.0 12/18/2014
PCN03A-14 FAQ
PCN03A-14 1.0 4/4/2014
PCN03A-14 Material Set Table
PCN03A-14 1.0 4/4/2014
PCN05A-14 FAQ
PCN05A-14 1.0 6/6/2014
PCN03A-14 Affected Part Number List
PCN03A-14 1.0 4/4/2014
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-14 1.0 11/21/2014
PCN07A-14 Automotive XO foundry transfer
PCN07A-14 1.0 12/18/2014
PCN14A-09 Notification of Intent to Utilize AQAS and AQMS for MachXO 324-ftBGA Devices
PCN14A-09 1 8/1/2009
PCN14A-09 MachXO2280 324-ftBGA ASEM AQAS AQMS - Japanese Language
PCN14A-09 1 8/1/2009
PCN02A-15 Frequently Asked Questions
2.0 6/18/2015
PCN 02A-15 Affected_OPN_Listing
Discontinuance 		3.0 8/12/2015
PCN 02A-15 SnPb and Select Mature Family Discontinuance
1.0 6/18/2015
PCN05A-17 Halogen-Free substrate at ASEM
1.2 10/27/2017
PCN05A-17 Affected Parts List
1.0 1/1/0001
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		6.7 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO Product Brief
I0176 7.0 1/14/2013
MachXO Product Brief (Chinese)
I0176C 8.0 1/14/2013
MachXO Control Development Kit Brochure
I0206 1.0 10/19/2009
MachXO Mini Development Kit Product Brief
I0199 1.0 2/23/2009
MachXO Product Brief (Japanese)
I0176J 7.0 4/2/2010
Product Selector Guide
I0211 26.0 7/9/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice MachXO Product Family Qualification Summary
Deleted last three pages 		H 1/23/2015
FTN256_LAXP2_LAMXO
Rev F 1/30/2020
FTN324_LAMXO
Rev D 1/30/2020
TN100_LAMXO
Rev B 4/19/2018
TN144_LA
Rev C 4/25/2018
TN_TG_TQ144 Cu_wire all
Rev E 7/24/2018
FTN324
Rev N 1/30/2020
MN100_XO
Rev O 1/30/2020
TN_TG100 Cu_wire all
Rev D1 8/22/2018
MN132_Cu_all
Rev P 1/30/2020
FTN256_v1_Cu_XO_XP2
Rev. Q 5/20/2020
BN256_XO
Rev Q 6/25/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Creating An ADC Using FPGA Resources
1.0 3/1/2010
Expanding Microprocessor Connectivity Using Low-cost FPGAs
1.0 8/28/2013
Dual Sensor Design Solution - White Paper (Chinese Language Version)
1.0 5/31/2012
Pre-tested Design Accelerates Development (Korean Language)
1.0 3/1/2010
Pre-tested Design Accelerates Development (Chinese Language)
1.0 6/28/2010
Pre-tested Design Accelerates Development
1.0 3/1/2010
Pre-tested Design Accelerates Development (Traditional Chinese Language)
1.0 6/28/2010
The Challenges of Automotive Vision Systems Design
4/1/2007
MachXO: Platform Management Using Low-Cost Non-Volatile PLDs
2/23/2009
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages (Chinese Language)
1.0 7/1/2010
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages
1.0 7/1/2010
MachXO PLDs in System Control Designs
1.0 10/19/2009
MachXO: Platform Management Using Low-Cost Non-Volatile PLDs (Chinese Language)
1.0 6/8/2009
ispMACH 4000ZE Practical Low Power CPLD Design
8/25/2009
MachXO: Optimized Programmable Devices for Bus Interfaces, Bridges and Control
7/1/2005
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LCMXO640E csBGA 100
1.04 4/16/2008
[BSDL] LCMXO2280C caBGA 256
1.00 6/29/2009
[BSDL] LCMXO640E TQFP 144
1.04 4/16/2008
[BSDL] LCMXO640E csBGA 132
1.04 4/16/2008
[BSDL] LCMXO2280C ftBGA 324
1.03 4/16/2008
[BSDL] LCMXO2280C TQFP 100
1.03 4/16/2008
[BSDL] LCMXO2280E TQFP 100
1.03 4/16/2008
[BSDL] LCMXO1200C TQFP 100
1.02 4/16/2008
[BSDL] LCMXO640C TQFP 144
1.04 4/16/2008
[BSDL] LCMXO2280C ftBGA 256
1.03 4/16/2008
[BSDL] LCMXO1200E TQFP 144
1.03 4/16/2008
[BSDL] LCMXO1200E ftBGA 256
1.02 4/16/2008
[BSDL] LCMXO2280E ftBGA 256
1.03 4/16/2008
[BSDL] LCMXO2280E ftBGA 324
1.03 4/16/2008
[BSDL] LCMXO1200C TQFP 144
1.03 4/16/2008
[BSDL] LCMXO640C csBGA 132
1.04 4/16/2008
[BSDL] LCMXO256C csBGA 100
1.04 4/16/2008
[BSDL] LCMXO640C csBGA 100
1.04 4/16/2008
[BSDL] LCMXO640C fpBGA 256
1.04 4/16/2008
[BSDL] LCMXO2280C csBGA 132
1.03 4/16/2008
[BSDL] LCMXO1200C ftBGA 256
1.02 4/16/2008
[BSDL] LCMXO1200E csBGA 132
1.03 4/16/2008
[BSDL] LCMXO640E TQFP 100
1.04 4/16/2008
[BSDL] LCMXO1200C caBGA 256
1.00 6/29/2009
[BSDL] LCMXO640E caBGA 256
1.00 6/29/2009
[BSDL] LCMXO640C ftBGA 256
1.04 4/24/2008
[BSDL] LCMXO640C caBGA 256
1.00 6/29/2009
[BSDL] LCMXO640E fpBGA 256
1.04 4/16/2008
[BSDL] LCMXO2280C TQFP 144
1.03 4/16/2008
[BSDL] LCMXO256C TQFP 100
1.04 4/16/2008
[BSDL] LCMXO1200C csBGA 132
1.03 4/16/2008
[BSDL] LCMXO2280E csBGA 132
1.03 4/16/2008
[BSDL] LCMXO2280E TQFP 144
1.03 4/16/2008
[BSDL] LCMXO640C TQFP 100
1.04 4/16/2008
[BSDL] LCMXO256E csBGA 100
1.04 4/16/2008
[BSDL] LCMXO1200E caBGA 256
1.00 6/29/2009
[BSDL] LCMXO2280E caBGA 256
1.00 6/29/2009
[BSDL] LCMXO1200E TQFP 100
1.02 4/16/2008
[BSDL] LCMXO640E ftBGA 256
1.04 4/24/2008
TITLE NUMBER VERSION DATE FORMAT SIZE
XO Device Family DELPHI Models
1.0 9/3/2009
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] Lattice MachXO
2.2 9/1/2009 IBS 25.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO 2280 Breakout Board Evaluation Kit - OrCAD Capture Schematic Source
Design Entry (.dsn) format schematics for the MachXO 2280 Breakout Board. 		1.0 3/21/2011
POWR1014A Breakout Board OrCAD Schematic Source
Design Entry (.dsn) format schematics for the POWR1014A Breakout Board. 		1.0 3/21/2011
POWR1014A Breakout Board PCB Artwork
PCB Design (.brd) format PCB artwork and PDF for the POWR1014A Breakout board. 		1.0 3/21/2011
MachXO 2280 Breakout Board PCB Artwork
PCB Design (.brd) format PCB artwork and PDF for the MachXO 2280 Breakout board. 		1.0 3/21/2011
BGA Breakout and Routing Example #1 - MN100
TN1074 1.0 12/29/2009
BGA Breakout and Routing Example #2 - MN132
TN1074 1.0 12/29/2009
BGA Breakout and Routing Example #2 - MN100
TN1074 1.0 12/29/2009