I/O Interface IP Core

Enables Access to External Modules via Standard Interfaces

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The I/O Interface IP provides a set of I/O functions that enable access to external modules through standard interfaces such as Advanced High-performance Bus Lite (AHB-Lite) and Advanced extensible Interface Lite (AXI4-Lite). This IP supports up to 256 bits of general-purpose input and output ports.

Resource Utilization details are available in the IP Core User Guide.

Features
  • Supports either AHB-Lite or AXI4-Lite interface to I/O Bus Interface
  • Supports 8, 16, or 32-bit data access for the AHB-Lite interface. For the AXI4-Lite interface, the data access is fixed at 32 bits
  • Supports up to 256 bits of general purpose input and output ports that can be programmed and sampled

Block Diagram

IO Interface放大图片

Ordering Information

The I/O Interface IP is provided at no additional cost with the Lattice Radiant software

Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
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I/O Interface IP Core - User Guide
FPGA-IPUG-02292 1.1 12/11/2025 PDF 1.2 MB
标题 编号 版本 日期 格式 文件大小
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I/O Interface IP Core - Release Notes
FPGA-RN-02084 1.1 12/11/2025 PDF 237.9 KB

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