Low-Power General Purpose FPGA

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Industry-leading I/O Count in Small Packages – Up to 2x more I/O per mm2 vs. similar FPGAs, in packages as small as 6x6 mm, with support for PCIe and GigE (SGMII).

High-speed Interfaces – Up to 70% faster differential I/O (vs. similar FPGAs) at 1.5 Gbps. 5 Gbps PCIe, 1.25 Gbps SGMII (GigE) and 1066 Mbps DDR3 memory interfaces also supported.

Built on Lattice Nexus platform – Up to 4x lower power vs. similar FPGAs. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.



  • Up to 39K logic cells, 2.9 Mb embedded memory, 56 18 x 18 multipliers, 192 programmable I/O, one lane of 5 Gbps PCIe, two lanes of 1.25 Gbps SGMII, two ADCs (each 12-bit, 1 MSPS).
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Instant-on configuration – I/O configures in 3 ms, and full-device as fast as 8 ms.
  • Available in Commercial, Industrial and Automotive (AEC-Q100 qualified) temperature grades.

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Certus-NX Device Selection Guide
Features LFD2NX-17 LFD2NX-40
Logic Cells 17K 39K
Embedded Memory (EBR) Bits (kb) 432 1512
Large Memory (LRAM) Bits (kb) 2560 1024
18 X 18 Multipliers 24 56
ADC Blocks 2 2
GPLL 2 3
5 Gb/s PCIe Gen2 Hard IP 1
Full-chip Configuration Time1 (ms) 8 14
I/O Configuration Time1 (ms) 3 3
Temperature Grades2
C, I, A C, I, A
0.5 mm Total I/O (Wide Range, High Performance, ADC4) / PCIe Lane5

121 csfBGA (6 x 6 mm)3 77 (23, 48, 6) / 0 81 (23, 58, 0) / 1
0.8 mm Total I/O (Wide Range, High Performance, ADC4) / PCIe Lane5

196 caBGA (12 x 12 mm) 156 (92, 58, 6) / 0
256 caBGA (14 x 14 mm)3 191 (111, 74, 6) / 1

1. QSPI mode at 150 MHz nominal frequency
2. C = Commercial, I = Industrial, A = Automotive
3. Available in Automotive Grade
4. Each ADC pin count reflects using dedicated complement pair and vRef
5. Each PCIe lane consists of a Tx and Rx complement pair

Example Solutions

PCIe to SGMII Bridge

  • Bridge processor to SGMII via PCIe Gen2
  • Compact packages as small as 6x6 mm with PCIe and SGMII support
  • Hard blocks for PCIe Gen2 and SGMII CDR eases development

PCIe Control Plane Bridge

  • Bridge processor via PCIe Gen2 to multiple control plane peripherals (UART, SPI, I2C, MDIO, etc.) and board management functions
  • Packages with high # of programmable I/O per mm2 maximizes # of interfaces in a given form-factor
  • PCIe hard IP with built-in Multi-function support simplifies development
  • Instant-on configuration supports board management needs and PCIe boot-time requirements


  • Off-load CPU by using Certus-NX as a co-processor to accelerate complex functions
  • DDR3 & LPDDR2 interface support (up to 1066 Mbps) and on-chip embedded memory (up to 2.9 Mbit) provide multiple options for data buffering
  • Compact packages as small as 6x6 mm with PCIe and DDR memory interface support

Motor Control

  • Increase efficiency and performance of motor control functions
  • High reliability due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology
  • Industrial temperature support

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