Generic Soft SPI Master Controller

Industry standard interface - The Serial Peripheral Interface (SPI) bus provides an industry standard interface between processors and other devices. This reference design is designed to provide an interface between a generic processor with parallel bus interface and external SPI devices.

Compatible with all SPI Modes - SPI interface is a good choice for designs that require full-duplex capability for sending and receiving data at the same time. The SPI Master Controller can communicate with multiple off-chip SPI ports and can also be configured to support all modes of CPOL and CPHA (00, 01, 10, and 11).

Complete Reference Design and Demo - Training dataset, project & source files, demo files and test bench are provided to enable modification.

Features

  • Supports a wide array of Lattice FPGAs such as MachXO2™, MachXO3™, LatticeECP3™, ECP5™, CrossLink™, CrossLink™-NX, and iCE40 UltraPlus™
  • Provision for easy integration of any processor interface
  • Up to five slave select outputs
  • Configurable timing features for timing-sensitive slave devices

Block Diagram

Documentation

快速参考
技术资源
下载
标题 编号 版本 日期 格式 文件大小
Generic Soft SPI Master Controller Demo - Documentation
FPGA-UG-02123 1.0 1/1/2021 PDF 1.6 MB
标题 编号 版本 日期 格式 文件大小
Generic Soft SPI Master Controller - Source Code
FPGA-RD-02209 1.0 1/1/2021 PDF 880.5 KB
Generic Soft SPI Master Controller - Documentation
FPGA-RD-02209 1.0 1/1/2021 PDF 880.5 KB
标题 编号 版本 日期 格式 文件大小
Generic Soft SPI Master Controller Demo - Source Code
FPGA-UG-02123 1.0 1/1/2021 ZIP 1.8 MB
Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.