Generic Soft SPI Master Controller Reference Design

Serial Peripheral Interface (SPI) Master Controller Reference Design

Industry standard interface - The Serial Peripheral Interface (SPI) bus provides an industry standard interface between processors and other devices. This reference design is designed to provide an interface between a generic processor with parallel bus interface and external SPI devices.

Compatible with all SPI Modes - SPI interface is a good choice for designs that require full-duplex capability for sending and receiving data at the same time. The SPI Master Controller can communicate with multiple off-chip SPI ports and can also be configured to support all modes of CPOL and CPHA (00, 01, 10, and 11).

Complete Reference Design and Demo - Training dataset, project & source files, demo files and test bench are provided to enable modification.

Features

  • Supports a wide array of Lattice FPGAs such as MachXO2™, MachXO3™, LatticeECP3™, ECP5™, CrossLink™, CrossLink™-NX, and iCE40 UltraPlus™
  • Provision for easy integration of any processor interface
  • Up to five slave select outputs
  • Configurable timing features for timing-sensitive slave devices

Block Diagram

Documentation

Quick Reference
Technical Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Generic Soft SPI Master Controller Demo - Documentation
FPGA-UG-02123 1.0 1/1/2021 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Generic Soft SPI Master Controller - Source Code
FPGA-RD-02209 1.0 1/1/2021 ZIP 833.5 KB
Generic Soft SPI Master Controller - Documentation
FPGA-RD-02209 1.0 1/1/2021 PDF 880.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Generic Soft SPI Master Controller Demo - Source Code
FPGA-UG-02123 1.0 1/1/2021 ZIP 1.8 MB
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