AXI4 Interconnect IP Core

A Parameterized Soft IP Offering High-Performance, Low-Latency AMBA 3 AHB-Lite Fabric

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The Lattice Semiconductor AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems. Any AXI4/AXI4-Lite compliant IP can be easily plug-and-play into the system for smooth integration. It supports different data width conversion and clock-domain-crossing. Furthermore, it supports multiple Managers with multiple memory-mapped Subordinates.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliance with AMBA AXI4 and AXI4-Lite Protocol
  • Fully parameterized design
  • Connection of multiple AXI4 Managers to multiple memory-mapped AXI4 Subordinates
  • Support up to 32 AXI4 or AXI4-Lite Managers and 32 AXI4 or AXI4-Lite Subordinates
  • Heterogeneous support - AXI4 and AXI4-Lite in single interconnect

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Block Diagram

AXI4 Interconnect Module Block Diagram放大图片

Ordering Information

The AXI4 Interconnect IP is provided at no additional cost with Lattice Propel Builder.

Documentation

快速参考
资讯资源
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AXI4 Interconnect IP Core - User Guide
FPGA-IPUG-02196 1.8 6/26/2025 PDF 914.1 KB
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AXI4 Interconnect IP Module - Release Notes
FPGA-RN-02045 1.2 12/11/2025 PDF 305.6 KB

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