[Blog] Navigating DO-254 Compliance in FPGA-Based Avionics

As modern avionics system complexity increases, safety certification has become one of the most demanding challenges hardware teams face. At the center of that challenge is DO-254, the worldwide standard that governs the development of airborne electronic hardware.

In a recent webinar, experts from Lattice and NewTec broke down what DO-254 compliance actually requires, where FPGA-based designs help simplify safety challenges, and how the right hardware partner can meaningfully reduce the burden of achieving certification.

What DO-254 Is and What It Demands
Published by RTCA (Radio Technical Coalition for Aeronautics) and EUROCAE (European Organization for Civil Aviation Equipment) as DO-254/ED-80, the standard applies to all programmable hardware in airborne systems and is required for any hardware above Design Assurance Level (DAL) C in civil aviation certification. It is not a checklist. It is a process-based framework that demands documented evidence of rigor at every stage of product development, structured around five Design Assurance Levels – DAL A through E – that scale requirements based on the severity of a potential failure.

A typical DO-254 program could run 12 to 18 months and is structured around four formal Stage-of-Involvement (SOI) audits with certification authorities. The development process follows a V-model in which every design artifact must have a corresponding verification artifact. Traceability is bidirectional and non-negotiable: retrofitting it at the end of a program multiplies effort by three to five times compared to maintaining it from day one. The Plan for Hardware Aspects of Certification functions as the master agreement between the development team and the certification authority and should be agreed upon early and updated continuously throughout the program.

Why FPGAs Are Well-Suited for DO-254 Programs
FPGAs have become the hardware platform of choice for many avionics programs, and for good reason. Their flexibility enables complex control, interface, signal processing, and safety functions to be implemented and updated without the cost and lead time of custom silicon. Their reconfigurability allows design teams to respond to evolving requirements across a certification lifecycle. And their ability to implement self-contained, independently verifiable logic blocks maps well to the modular, traceable development approach that DO-254 demands.

That said, realizing these benefits in a certified program requires careful attention to a few specific areas:

• Flexibility. While an asset for system designers, an FPGA's reconfigurability also creates certification complexity, as every configurable element must be fully specified, traced, and verified.
• Tool qualification. Lattice EDA design tools such as HDL compilers, synthesizers, and place-and-route tools require formal qualification because errors can propagate undetected into the design. Every tool change mid-project triggers re-assessment, making toolchain stability a program management priority.
• IP selection. Pre-existing IP used in a DO-254 effort must satisfy EASA AMC 20-152A objectives covering selection, provider data assessment, errata management, verification strategy, and field use. Choosing vendor IP with existing documentation and verified evidence dramatically reduces the additional work required.

Why FPGA Partner Selection Matters
The right FPGA vendor does more than supply silicon in a DO-254 program. They reduce the verification surface, provide pre-qualified evidence, and support a design flow built for certification from the start.

Lattice brings decades of certified pedigree to this role, with devices already flying in DAL A and DAL B systems and billions of hours of field service. Purpose-built for airborne systems, Lattice FPGAs combine inherent radiation tolerance, hardened security, and a dedicated Anti-Tamper module in a low power, small form factor that keeps verification scope manageable and certification costs in check.

On the tools and flow side, Lattice supports a model-first approach with full bidirectional traceability from model through requirement, design, verification, test, and revision. Lattice EDA Design tools are TÜV-certified to IEC 61508 and ISO 26262, and built-in capabilities including SEU fault injection, automated Triple Modular Redundancy, and latch-up immunity reduce both design risk and the evidence burden teams carry into audits. For DAL A programs, Lattice provides a turnkey Assurance Data Package aligned to DO-254/ED-80 and AMC 20-152A, with 100% requirement to RTL coverage and demonstrated functional, elemental code coverage.

Field-Proven Best Practices from NewTec
Process decisions made early in a DO-254 program are the ones that most often determine whether certification stays on schedule or becomes costly to recover. Drawing on real program experience, NewTec identified where teams most commonly run into trouble and what to do differently.

The highest-impact changes happen before a single line of RTL is written. Requirements must be locked, testable, and specific before design begins, and certification authorities should be engaged at the planning stage rather than the audit stage. Traceability should be maintained as a living record throughout the program, not reconstructed at the end.

Verification is where underestimation is most costly. On DAL A programs it accounts for roughly half of total effort, yet teams routinely treat it as a final check. Automating regression testing early helps verification keep pace with design progress, and design partitioning can meaningfully reduce the DAL scope that needs to be verified in the first place.

Tool discipline is equally important. Changing tool versions mid-project requires re-assessment and can invalidate prior verification work. And for DAL A and DAL B, simulation alone is not sufficient – in-device testing on production-equivalent hardware is required.

Capable Hardware, Disciplined Execution, the Right Partner
DO-254 compliance is a combination of technical capacity and process discipline. The right FPGA reduces the verification surface, provides pre-built evidence, and supports a qualified, traceable design flow from day one.

Together, Lattice and NewTec offer avionics development teams both: purpose-built low-power FPGAs with decades of certified pedigree, and a consulting partner with deep experience navigating programs through SOI audits.

To watch the full webinar, click here, and to learn more about Lattice's avionics FPGA portfolio, contact our team today.