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Reference Design

I2C Master Controller

Implements an I2C Master Controller in Verilog

Reference Design

Soft I2C Bus Master

Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families

Reference Design

I2C to APB Bridge Reference Design

With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

Reference Design

I2C Master - WISHBONE Compatible

Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus

Reference Design

I2C Slave to SPI Master Bridge

Implements an I2C slave to SPI master bridge.

Reference Design

I2C Slave Peripheral using Embedded Function Block

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2

IP Core

SLS I2C Master IP Core

Ease to use I2C Master IP core from SLS. It comes with ready to use HAL driver, reference design and various documents.

Demo

Soft I2C Master and Slave – Simple Write and Read

Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.

IP Core

DI2CM: I2C Bus Interface - Master

Provides an interface between a microprocessor / microcontroller and an I2C bus

Reference Design

MachXO2 I2C Embedded Programming Access Firmware

Provides C code for interfacing to MachXO2 from a microcontroller, and RTL for implementing I2C between an external master and the MachXO2

IP Core

DI2CS: I2C Bus Interface - Slave

Provides an interface between a microprocessor/microcontroller and an I2C bus

IP Core

DI2CSB: I2C Bus Interface Slave - Base version

Provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus

FAQ

CrossLink-NX: Why does I2C Master Core IP does not have documentation about I2C repeated start?

Description:The I2C Master IP from Lattice does not support repeated start to allow a read then write or a write then read command.Solution:A workaround for this is to perform separate start-stop transactions, refer to FPGA-IPUG-02071 section 2.5.On the other hand, Lattice has a generic Soft…

IP Core

I2C Controller IP Core

Lattice Semiconductor general-purpose I2C Controller IP Core offers an effective way to control an I2C bus.

IP Core

I2C Target IP Core

Lattice I2C Target IP Core provides device addressing, read/write operation and an acknowledgement mechanism.

Reference Design

I2C Slave/Peripheral

Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment

Reference Design

MachXO5-NX I2C Reference Design

The MachXO5-NX I2C reference design initiates and connects the MachXO5-NX flash programming through the user I2C interface.

Reference Design

Soft I2C Slave Peripheral

Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families

Reference Design

SMBus Controller

Provides a bridge between the SMBus (System Management Bus) master and the WISHBONE bus. SMBus is a 2-wire interface similar to I2C.