I2C Controller IP Core

Flexible I2C Bus Control with Customizable FPGA-Based I2C Controller IP

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Lattice Semiconductor general-purpose I2C Controller IP offers an effective way to control an I2C bus. The programmable nature of FPGA provides you with flexibility of configuring the I2C Controller device to your need, thus allowing you to customize the I2C Controller to meet your specific design requirement.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports 7-bit and 10-bit Addressing Mode.
  • Programmable SCL frequency, supporting the following bus speeds:
    • Standard-mode (Sm) – up to 100 kbit/s
    • Fast-mode (Fm) – up to 400 kbit/s
    • Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up and Glitch Filter.
  • Arbitration lost detection in multi-controller system.

Block Diagram

I2C Controller IP Core Block DiagramExpand Image

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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I2C Controller IP User Guide
FPGA-IPUG-02071 2.0 7/15/2025 PDF 927.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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I2C Controller IP Core - Release Notes
FPGA-RN-02027 1.1 7/15/2025 PDF 223.8 KB

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