I2C Master IP Core

Control for I2C Bus Interface

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I2C (Inter-Integrated Circuit) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is commonly used in short-distance systems, where the number of traces on the board should be minimized. The device that initiates the transmission on the I2C bus is commonly known as the Master, while the device being addressed is called the Slave.

Lattice Semiconductor general-purpose I2C Master IP Core offers an effective way to control an I2C bus. The programmable nature of FPGA provides users with flexibility of configuring the I2C Master device to their needs, thus allowing users to customize the I2C Master Controller to meet their specific design requirements.

This design is implemented in Verilog. It can be targeted to CrossLink-NX™ FPGA devices and implemented using the Lattice Radiant Software Place and Route tool integrated with the Synplify Pro® synthesis tool.

Features

  • Supports 7-bit and 10-bit Addressing Mode with Programmable SCL frequency, supporting the bus speeds: Standard-mode (Sm) – up to 100 kbit/s, Fast-mode (Fm) – up to 400 kbit/s and Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up and Glitch filter
  • Arbitration lost detection in multi-master system
  • Polling and Out-of-band Interrupt Modes
  • Selectable LMMI or APB interface

Block Diagram

I2C Master IP Core Block DiagramExpand Image

Performance and Size

Avant Family
Configuration Clk Fmax (MHz)* Slice Registers LUTs EBRs
Default 115.168 508 587 0
APB Mode Enable is Unchecked,
Others = Default		 249.813 491 576 0
Implementation of FIFO = EBR,
Others = Default		 116.239 492 559 2
FIFO Depth = 256,
RX FIFO Almost Full Flag = 254,
Others = Default		 99.78 620 1164 0
FIFO Depth = 256,
RX FIFO Almost Full Flag = 254,
Implementation of FIFO = EBR,
Others = Default		 97.809 604 651 2
Nexus Family (CrossLink-NX)
Configuration Clk Fmax (MHz)* Slice Registers LUTs EBRs
Default 179.662 508 609 0
APB Mode Enable is Unchecked,
Others = Default		 200 489 652 0
Implementation of FIFO = EBR,
Others = Default		 190.876 494 584 2
FIFO Depth = 256,
RX FIFO Almost Full Flag = 254,
Others = Default		 137.893 623 1388 0
FIFO Depth = 256,
RX FIFO Almost Full Flag = 254,
Implementation of FIFO = EBR,
Others = Default		 190.949 604 697 2

Note: Fmax is generated when the FPGA design only contains I2C Slave IP Core and the target Frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I2C Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02071 1.7 8/25/2023 PDF 635.4 KB

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