SMBus Controller

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Reference Design LogoThe System Management Bus (SMBus) is a two-wire interface through which simple system and power management devices can communicate with the rest of the system. The protocol is compatible with the I2C bus protocol and is often found in monitoring power conditions, temperature, and other sensors on a board. This reference design provides a bridge between the SMBus master and the WISHBONE bus. A typical application of this design includes the interface between a WISHBONE-compliant, on-board microcontroller and multiple SMBus peripheral components.

While SMBus is derived from I2C, there are several major differences existing between the specifications of the two buses. The most significant differences between the two are the timeout and the minimum clock speed requirements. SMBus defines a clock-low timeout limit of 25 ms for master, 35 ms for slave, and a minimum clock speed of 10 KHz. I2C does not have such a requirement and the master or the slave can hold the bus low indefinitely. In addition, SMBus specifies a data hold time of 300 ns while the I2C hold time is 0. In terms of performance, SMBus operates up to 100 KHz, while I2C’s fast-mode supports up to 400 KHz. Other minor differences include voltage level and rise/fall time. The details can be found in the SMBus Specification and I2C Specification.

This design is based on Lattice reference design RD1046: I2C Master with WISHBONE Interface. It is available in both Verilog and VHDL languages.

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Block Diagram

SMBus Controller Block Diagram

Performance and Size

Tested Devices* Language Performance I/O Pins Design Size Revision
LCMXO2-2000HC-4TG100CES Verilog > 50 MHz 29 294 LUTs 1.0
LCMXO2-2000HC-4TG100CES VHDL > 50 MHz 29 285 LUTs 1.0
LCMXO1200C-3T100C Verilog > 50 MHz 29 299 LUTs 1.0
LCMXO1200C-3T100C VHDL > 50 MHz 29 290 LUTs 1.0

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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SMBus Controller Reference Design - Documentation
FPGA-RD-02100 1.1 1/22/2021 PDF 1.3 MB
SMBus Controller Reference Design Source Code
RD1098 1.0 11/8/2010 ZIP 2.2 MB

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