I2C Target IP Core

Configurable I2C Target IP for Flexible Device Addressing

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Lattice Semiconductor general-purpose I2C Target IP provides device addressing, read/write operation and an acknowledgement mechanism. The programmable nature of FPGA provides you with the flexibility of configuring the I2C Target device to any legal Target address, thus, avoiding a potential Target address collision on an I2C bus with multiple Target devices.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports 7-bit and 10-bit Addressing Mode.
  • Programmable SCL frequency, supporting the following bus speeds:
    • Standard-mode (Sm) – up to 100 kbit/s
    • Fast-mode (Fm) – up to 400 kbit/s
    • Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up and Glitch Filter.
  • Supports Clock stretching.

Block Diagram

I2C Target IP Core Block DiagramExpand Image

Resource Utilization

LAV-AT-500E-1LFG1156I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 107 320 394 0
APB Mode Enable: false,
Others = Default		 251 318 394 0
Implementation of FIFO = EBR,
Others = Default		 127 304 372 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 112 320 394 0
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 256,
RX FIFO Almost Full Flag: 256,
Others = Default		 105 350 910 0

Note: Fmax is generated when the FPGA design only contains I2C Target IP Core, and the target frequency is 50MHz. These values may be reduced when user logic is added to the FPGA design.

LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 168 319 397 0
APB Mode Enable: false,
Others = Default		 200 304 370 0
Implementation of FIFO = EBR,
Others = Default		 157 303 364 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 168 319 385 0
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 256,
RX FIFO Almost Full Flag: 256,
Others = Default		 167 349 1088 0

Note: Fmax is generated when the FPGA design only contains I2C Target IP Core, and the target frequency is 50MHz. These values may be reduced when user logic is added to the FPGA design.

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 101 319 385 0
APB Mode Enable: false,
Others = Default		 120 304 370 0
Implementation of FIFO = EBR,
Others = Default		 103 303 365 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 94 319 385 0
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 256,
RX FIFO Almost Full Flag: 256,
Others = Default		 101 349 1089 0

Note: Fmax is generated when the FPGA design only contains I2C Target IP Core, and the target frequency is 50MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I2C Target IP User Guide
FPGA-IPUG-02072 2.0 12/20/2024 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I2C Target IP Release Notes
FPGA-RN-02028 1.0 12/20/2024 PDF 217.7 KB

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