I2C Target IP Core

Configurable I2C Target IP for Flexible Device Addressing

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Lattice Semiconductor general-purpose I2C Target IP provides device addressing, read/write operation and an acknowledgement mechanism. The programmable nature of FPGA provides you with the flexibility of configuring the I2C Target device to any legal Target address, thus, avoiding a potential Target address collision on an I2C bus with multiple Target devices.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports 7-bit and 10-bit Addressing Mode.
  • Supports the following bus speeds:
    • Standard-mode (Sm) – up to 100 kbit/s
    • Fast-mode (Fm) – up to 400 kbit/s
    • Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Supports Clock stretching
  • Programmable ACK/NACK response on address and data phases
  • Integrated pull-up through FPGA I/O settings

Block Diagram

I2C Target IP Core Block DiagramExpand Image

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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I2C Target IP Core - User Guide
FPGA-IPUG-02072 2.3 6/26/2026 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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I2C Target IP Core - Release Notes
FPGA-RN-02028 1.3 6/26/2026 PDF 371.2 KB

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