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ID: 200
实例类型: faq
分类: Implementation
相关: Timing Analysis
产品系列: All FPGA

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How do I get a reasonable I/O timing report when PLL phase shift is very large?

When you change the PLL phase to improve the Tco, you can program the PLL phase delay by more than 180 degree, e.g. 315 degree. Its equivalent effect is to advance 45 degree if one clock cycle latency is acceptable. But the Lattice software will always regard it as the delay of 315 degree. Therefore the trace timing tool will add 7/8ths of a clock cycle to the clock insertion delay.


In order to get the expected timing result, you can use the PLL_PAHSE_BACK keyword to direct the trace timing tool to subtract 1/8th of a clock cycle from the clock insertion delay, i.e. advancing 1/8th of a clock cycle.


For example, when the PLL_PAHSE_BACK keyword is added, the CLOCK_TO_OUT preference can be something like "CLOCK_TO_OUT ALLPORTS 10.000000 ns CLKPORT "clk" PLL_PHASE_BACK". One thing to be noted is that the real Tco is one clock cycle later than in the trace report with this keyword. You must deal with this one-cycle latency for outputs when using this method.