The Platform Manager family can use Verilog or VHDL as a text entry method to develop user code. PAC-Designer is used to set up the analog functions but Verilog or VHDL can be used to describe the sequence and control logic. Using a Platform Manager within PAC-Designer also supports an entry flow using ispLEVER to describe the FPGA logic.
Link to PAC-Designer Software
ispLEVER Starter Software