MIPI CSI-2 to PCIe Reference Design

Features

• The Lattice MIPI CSI/DSI RX IP in this reference design is configured to support two or four lanes with lane rate of 1200 Mbps, as capped by IMX258 capability. The IP receives, processes, and converts incoming MIPI video payload packets up to 4K30 into Unified Video Streaming Interface (UVSI) packets.
• The Lattice PCIe x4 IP provides DMA engine to perform data transfer between FPGA and host PC through PCIe Gen3x4 link. The IP is configured in DMA Bridge mode, providing an AXI4 interface that enables camera control from the host PC.
• The Lattice Debayer IP Core extracts the R, G, and B components from the pixel data output by the image sensor, converting the RAW10 data format into full RGB components.
• The Lattice Color Correction Matrix IP Core perform pixel data correction by adjusting R, G, and B components gain and compensate for color channel crosstalk.
• The Lattice Automatic White Balance IP Core automatically compensates for illumination temperature-based color differences in bayer domain, such that white actually appears white.
• The Unified Video to PCIe bridge maps UVSI packets to PCIe DMA AXI-S packets.