MIPI CSI-2 to PCIe Reference Design

Transferring MIPI Camera Serial Interface-2 to Computer via PCIe

The CertusPro™-NX Mobile Industry Processor Interface (MIPI®) Camera Serial Interface-2 (CSI-2) to Peripheral Component Interconnect Express (PCIe®) reference design demonstrates the functionality of transferring MIPI CSI-2 sensor video data to a computer through PCIe with a Direct Memory Access (DMA) engine. Built on the CertusPro‑NX Versa Board, this design includes Linux Operating System (OS) driver support. It showcases the complete data path—from capturing sensor data, transferring it into the computer memory via PCIe and DMA, to rendering the video on the computer screen through the provided software driver.

Features

  • The Lattice MIPI CSI/DSI RX IP in this reference design is configured to support two or four lanes with lane rate of 1200 Mbps, as capped by IMX258 capability. The IP receives, processes, and converts incoming MIPI video payload packets up to 4K30 into Unified Video Streaming Interface (UVSI) packets.
  • The Lattice PCIe x4 IP provides DMA engine to perform data transfer between FPGA and host PC through PCIe Gen3x4 link. The IP is configured in DMA Bridge mode, providing an AXI4 interface that enables camera control from the host PC.
  • The Lattice Debayer IP Core extracts the R, G, and B components from the pixel data output by the image sensor, converting the RAW10 data format into full RGB components.
  • The Lattice Color Correction Matrix IP Core perform pixel data correction by adjusting R, G, and B components gain and compensate for color channel crosstalk.
  • The Lattice Automatic White Balance IP Core automatically compensates for illumination temperature-based color differences in bayer domain, such that white actually appears white.
  • The Unified Video to PCIe bridge maps UVSI packets to PCIe DMA AXI-S packets.

Block Diagram

MIPI CSI-2 to PCIe Reference DesignExpand Image

MIPI CSI-2 to PCIe Reference Design Block Diagram


Documentation

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MIPI CSI-2 to PCIe Reference Design
To learn more about this product design and to access the complete source code, bitstream and user guide in GitHub, please click here 		3/26/2026 WEB

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