POS PHY Level 3链路

Edge AI Accelerated Object Detection On FPGA

LatticeReferenceDesign-LogoPOS PHY Level 3规范定义了物理层(PHY)设备和链路层设备的互连,实现了Packet over SONET(POS)。POS PHY Level 3接口涵盖了所有应用,比特率高达2.4 Gbit/s。该规范确定了用于链路层设备的设计特点和要求。该设计在实现了一个POS PHY Level 3链路层接口的同时,还可以用于与通用FIFO通信。它的目的是使用户应用(链路层设备)通过基于该规范的接口和通用FIFO连接。

Features

  • Instantly identify and classify defects, enabling rapid response and corrective action
  • Efficient AI models optimized for edge devices, supporting continuous inspection
  • Supports a wide range of defect types and deployment scenarios
  • Easily connects to existing inspection systems and legacy infrastructure
  • Accurate detection for improved product quality and reduced waste

Block Diagram

Defect Detection Reference Design Block Diagram