10G Ethernet IP Core

Ethernet Transmission of Data Frame Compliant to the IEEE 802.3-2012 Standard

The Lattice Semiconductor 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 10GbE IP core consists of the 10-Gigabit Media Independent Interface (XGMII), which connects media access controllers (MACs) and Physical Layer devices (PHYs). The main function of the 10GbE MAC is to ensure that the media access rules specified in the 802.3 IEEE standards are met while transmitting a frame of data over an Ethernet.

IP Options:

CertusPro™-NX : MAC only, PHY only, MAC + PHY + 15881, and MAC + PHY

Avant™-G and Avant™-X: MAC only, PHY only, MAC + PHY

Resource Utilization details are available in the IP Core User Guide.

Features

MAC

  • Compliant to the IEEE 802.3-2012 standard
  • Supports standard 10 Gbps Ethernet link layer data rate
  • 64-bit wide internal datapath operating at 156.25 MHz
  • AXI4-Stream interface on the client’s transmit and receive interfaces
  • Supports deficit idle count (DIC)

PHY

  • Designed to the IEEE 802.3-2012 10GBASE-R specification
  • 64b/66b encoding and decoding
  • XGMII interface: 64-bit, 156.25 MHz
  • Supports AXI4-Lite and management data input/output for PCS
  • TX phase FIFO and RX clock compensation FIFO (CertusPro-NX devices only)

MAC + PHY + 1588 (CertusPro-NX)

  • Timestamping support as specified in the IEEE 1588v2 (2-step mode)

Jump to

Block Diagram

Ordering Information

  Part Number
Device Family Single Seat Perpetual Single Seat Annual
CertusPro-NX ETHER-10G-CPNX-UT ETHER-10G-CPNX-US
Avant-G ETHER-10G-AVG-UT ETHER-10G-AVG-US
Avant-X ETHER-10G-AVX-UT ETHER-10G-AVX-US

Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
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2.5G, 10G, and 25G Ethernet Driver API Reference
FPGA-TN-02375 1.1 6/26/2025 PDF 633.3 KB
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10G Ethernet IP Core - User Guide
FPGA-IPUG-02245 1.7 10/10/2025 PDF 5.7 MB
标题 编号 版本 日期 格式 文件大小
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10G Ethernet IP Core - Release Notes
FPGA-RN-02031 1.2 10/10/2025 PDF 277.8 KB