IP ExpressSPI4知识产权(IP)核在莱迪思可编程门阵列(FPGA)中实现了符合OIF标准的系统数据包接口第4级第2阶段版本1(SPI4.2.1)的用户实例化内核。SPI4 IP核支持多达256个数据通道和3到12.8Gbps的总吞吐量,用于连接带有OC192成帧器的网络处理器、映射器和逻辑结构,以及千兆和10千兆以太网MAC。

Features

  • The Soft SPI4 IP core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) interface standard
  • Supported through Diamond or ispLEVER IPexpress™ tool for easy user configuration and parameterization
  • Supports up to 256 independent channels
  • 400 to 500MHz DDR Dynamic mode operation in LatticeSC and LatticeSCM devices
  • 156 to 350MHz DDR Static timing mode operations for LatticeECP3 devices. Supports non-standard “SPI4 Lite” line rates.
  • Supports both 64b and 128b internal architectures for optimization of either speed or size
  • Requires only ~2000 slices (64b mode) for a full 256-channel Static mode core
  • Supports full bandwidth utilization of the SPI4 line in both directions - requires no idle cycles in the receive direction or insertion of idles in the transmit direction between bursts (as long as there is data available)
  • Parity error checking/generation on all receive and transmit control and data words (DIP4) and status (DIP2) interfaces
  • Parity error force capabilities on data (independent controls: control word and data) and status interfaces
  • Various run-time user controls
    • Force idles (transmitter)
    • Enable/disable packing (transmitter)
    • Training pattern (CAL_M, MAX_T)
  • Complete run-time programmability of all internal FIFO thresholds for efficient management of SPI4 line in terms of Lmax and packing
  • Provides a direct interface to primary device I/O at the SPI4 interface and an internal FIFO interface to user logic
  • Supports minimum transmit burst sizes in increments of 16 bytes from 16 bytes up to 1008 bytes for optimized network processor applications
  • Support for packet sizes down to 4 bytes in length
  • Fully configurable 512-location calendar RAM for Rx and Tx directions and associated 256-location status RAMs
  • Two independently configurable methods of status reporting in the receive and transmit directions - RAM addressable and Transparent
  • Rising or falling edge selectable Status Channel I/O independently configurable in the receive and transmit directions

The SPI4 is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Jump to

Block Diagram

性能和大小

LatticeECP31
配置 SLICE LUT REG I/O EBR 线速率(MHz)
总线宽度 状态模式
64 Transparent 2324 2600 3206 80 12 312
128 RAM 3967 4327 5185 80 18 350

1.性能和资源使用情况数据是通过使用LFE3-70EA-8FN672CES器件和Lattice Diamond 1.0和Synplify Pro D-2009.12L-1软件测得的。当使用不同软件版本或者LatticeECP3系列中不同密度或速度级的器件实现该设计,性能可能会有所不同。

LatticeSC/M1
配置 SLICE LUT REG I/O EBR 线速率(MHz)
总线宽度 状态模式
64 Transparent 2405 5126 3001 80 12 400
128 RAM 4015 5126 4840 80 18 400

1.性能和资源使用情况数据是通过使用LFSC3GA25E-6FF1020C器件和Lattice Diamond 1.0以及Synplify Pro D-2009.12L-1软件测得的。当使用不同软件版本或者LatticeSC/M系列中不同密度或速度级的器件实现该设计,性能可能会有所不同。

订购信息

系列 部件编号
LatticeECP3 SPI-42-E3-U3
LatticeSC/M SPI-42-SC-U3

IP版本:2.8

评估:欲下载该IP的完整评估版,请访问IPexpress工具并点击工具条上的IP服务器按钮。上面显示了所有可供下载的LatticeCORE IP核和模块。欲了解更多查看/下载IP核的信息,请阅读IP Express快速入门指南

购买:欲了解如何购买IP核,请联系您本地的莱迪思销售办事处

文档

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
选择全部
Soft SPI4 IP Core User's Guide
IPUG59 01.7 9/16/2010 PDF 1.8 MB
标题 编号 版本 日期 格式 文件大小
选择全部
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB