D16750：带有FIFO的可配置UART

Features

• Software compatible with 16450, 16550 and 16750 UARTs
• Configuration capability
• Separate configurable BAUD clock line
• Two modes of operation: UART mode and FIFO mode
• Majority Voting Logic
• In the FIFO mode transmitter and receiver are each buffered with 16 byte or 64 byte FIFO to reduce the number of interrupts presented to the CPU
• Optional FIFO size extension to 128, 256 or 512 Bytes
• Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
• In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Independently controlled transmit, receive, line status, and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Programmable automatic Hardware Flow Control logic through Auto-RTS and Auto-CTS
• Fully programmable serial-interface characteristics:
  • 5-, 6-, 7-, or 8-bit characters
  • Even, odd, or no-parity bit generation and
    detection
  • 1-, 1.5-, or 2-stop bit generation
  • Baud generation
• Complete status reporting capabilities
• Line break generation and detection.
• Internal diagnostic capabilities:
  • Loop-back controls for communications link
    fault isolation
  • Break, parity, overrun, framing error
    simulation
• Two DMA Modes allows single and multitransfer
• Technology independent HDL Source Code
• Full prioritized interrupt system controls
• Fully synthesizable static design with no internal tri-state buffers

Applications

• Serial Data communications applications
• Modem interface