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FPGA Design Constraints – Performance and Analysis to Achieve Design and Timing Closure

FPGA design constraints - performance and analysis to achieve design and timing closure

Posted 12/15/2021 by Roger Do, Senior Product Manager, Design Tools, Lattice Semiconductor

Traditionally, FPGA design was simple. Designers set a basic clock constraint that was propagated across the chip. But now, FPGA designs have become much more complex. There are multiple clocks, and relationships between those clocks. There may be clock domain crossings that need to be accounted for. So, FPGA design tools today must feature much greater analysis capabilities to show the designer, for example, where those clock domain crossings are, to be able to constrain for multiple clocks, an...

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The Criticality of Ethical AI

The Criticality of Ethical AI

Posted 12/09/2021 by Bob O’Donnell, President and chief analyst, Technalysis Research

One of the most exciting topics in the tech world is Artificial Intelligence, or AI. From its science-fiction like promise of intelligent machines to its more practical implementations as additional smarts in connected devices, AI is one of the most powerful technologies now available. But, as the well-known Peter Parker principle dictates, “With great power comes great responsibility” and so it is with AI. Companies building AI-enabled products and services, in particular, have star...

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Lattice sensAI Stack Enables Next Generation Edge AI Experiences

Posted 11/10/2021 by Hussein Osman

The AI/ML revolution continues to gain traction across multiple applications, particularly Edge applications. Edge devices like security cameras, robots, industrial equipment, Client PCs, and even toys can now support AI/ML capabilities that provide users with new capabilities and experiences. According to industry analyst firm ABI Research, the Edge AI chipset market “has experienced strong growth in the past and is expected to continue to grow to US$71 billion by 2024, with a CAGR of 31%...

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Lattice FPGAs Power Award-winning Hyperloop Design

Posted 09/30/2021 by David Thomas

Lattice low power FPGA technology helped the Swissloop design team engineer an award-winning hyperloop pod.

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Key Advantages of Choosing FPGAs Over MCUs

Posted 09/24/2021 by Jay Aggarwal

This Lattice blog will compare and contrast some of the key differences between FPGAs and their primary competition, microcontrollers (MCUs).

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Interfacing with SPI Devices, Part 2

Posted 09/23/2021 by Eugen Krassin

This blog post focuses on how to implement a clock domain SPI interface between a DAC and a Lattice FPGA.

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Memory Flexibility Key to FPGA-Based Designs

Posted 09/13/2021 by Bob O'Donnell

Combining Micron LPDDR4 memory with Lattice FPGAs can enable Edge applications with low power consumption and strong performance characteristics.

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Interfacing with SPI Devices, Part 1

Interfacing with SPI Devices, Part 1

Posted 09/07/2021 by Eugen Krassin

This blog post focuses on how to implement a two clock domain SPI interface between a DAC and a Lattice FPGA.

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Lattice Certus-NX FPGAs Optimized for Automotive Applications

Lattice Certus-NX FPGAs Optimized for Automotive Applications

Posted 08/25/2021 by Juju Joyce

Lattice Certus-NX general purpose FPGA family now offers automotive grade versions of its FPGAs that are AEC-Q100 qualified for use in wide range of automotive applications.

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Redefining the FPGA for Aerospace and Defense by Solving SWaP-C Challenges

Redefining the FPGA for Aerospace and Defense by Solving SWaP-C Challenges

Posted 08/24/2021 by Luke Miller

Learn how FPGAs can help address size, weight, power, and cost challenges for aerospace and defense applications.

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