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PCI Express Demos for the LatticeECP3 Versa Evaluation Board

Using a web browser, go to the LatticeECP3 Versa Evaluation Board Setup (Windows) page, and download the Windows setup.exe file: DK-ECP3-PCIE-setup.exe. 2. Double-click on the DK-ECP3-PCIE-setup.exe file. 3.

Document

PCI Express Demos for the ECP5 PCI Express Development Board User’s Guide

Using a web browser, go to the ECP5 PCI Express Board Setup (Windows) page, and download the Windows setup.exe file: DK-ECP5-PCIE-setup.exe. 2. Double-click on the DK-ECP5-PCIE-setup.exe file. 3. If the Install Program as Other User dialog appears, choose to install as the current…

Document

PCI Express Demos for the ECP5 and ECP5-5G Versa Development Board User Guide

User Manual FPGA-UG-02006 1.5 PDF 0.8MB

Document

ECP5 PCI Express Development Kit Quick Start Guide

To run the PCI Express Basic Demo, go to C:\Lattice_DevKits\KD-ECP5-PCIE-010\ Demonstration\PCIeBasic\, run PCIeBasic. bat. 2. The 14-Segment Control window in the demo allows interactive control of the LEDs display on the board.

Demo

CSI-2 PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 camera video data to computer via PCIe with a Direct Memory Access (DMA) engine.

IP Core

PCIe High-Channel-Count DMA IP Core

The HCC DMA IP core is a powerful PCIe DMA Engine with multiple industry standard AXI Interfaces. It is based on the Lattice PCIe HardIP.​

Document

CrossLink-NX PCIe Bridge Board Quickstart Guide

Doing more with the CrossLink-NX PCIe Bridge Board Check the Lattice Website at www.latticesemi.com/crosslink-nx-pcie-bridge to download the complete User’s Guide, additional Demonstrations and other Resources.

Demo

Lattice mVision DisplayPort to PCIe Demonstration

DisplayPort to PCIe bridge design demonstrates the functionality of transferring DisplayPort video data to a computer through PCIe with a DMA engine.

Board

CertusPro-NX PCIe Bridge Board

The CertusPro-NX PCIe Bridge Board enables video bridge capabilities to PCIe and embedded vision type applications.

Board

CrossLink-NX PCIe Bridge Board

Connectivity Development Platform Enabling Bridging of Multi-Standard I/O Interfaces to PCIe

IP Core

AXI to PCIe Bridge IP Core

The AXI to PCIe Bridge IP core translates AXI4 into PCIe transactions for shared memory or peer-to peer-applications. It is based on the Lattice PCIe Hard IP.

Board

Lattice Avant G70 PCIe Mini-Board

Avant G70 PCIe Mini-Board with Lattice Avant-G FPGA supports AI, video & industrial use with PCIe, SFP+, FMC, MIPI, memory, clock & more high-performance tasks.

Demo

SLVS-EC Sensor to PCIe Bridge Demonstration

The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.

Document

IP Suites for LatticeECP3 - News Brief

. • PCI Express Endpoint x1 / x4 • PCI Express Root Complex Lite x1 / x4 • PCI Master/Target 32-bit / 64-bit • PCI Target 32-bit / 64-bit • Scatter Gather DMA $995 $99 DS-PCIE- ST-U1 Ethernet Comprehensive Ethernet networking solutions. • 10Gb+ Ethernet MAC • Scatter Gather DMA • SGMII &…

Demo

Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 sensor video data to a computer through PCIe with a Direct Memory Access (DMA) engine.

FAQ

PCIe for Nexus FPGAs: How to access PCIe peripherals using AHB-lite interface?

Solution:DMA support must be enabled to access the PCIe endpoint through AHB-lite.The DMA (Direct Memory Access) support has an option to enable efficient data transfer when the device acts as an initiator or a master.For more information, refer to DMA Support section in the FPGA-IPUG-02091…

Demo

PCIe Basic Demo for Lattice Nexus-based FPGAs

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.

Reference Design

SLVS-EC Sensor to PCIe Bridge Reference Design

SLVS-EC to PCIe reference design allows the quick interface to receive serial data from CMOS Image Sensors & convert to DMA/PCIe Subsystem data format.

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

5G Mid-Power Integrated Small Cell, reference platform is a comprehensive development board tailored for 5G baseband processors and transceiver frontends.

FAQ

PCIe for Nexus FPGAs: What is the size of the Transmit Buffer and Receive Buffer in PCIe X1 IP Core and PCIe X4 IP Core?

The Transmit Buffer and Receive Buffer size is 2 kByte each.These RAM buffer sizes are fixed because it is a Core internal RAM, so the negotiated Maximum Payload Size (MPS) size will determine how many TLPs can be stored.For instance, in the Receive Buffer, if MPS is low, more TLPs can be stored, if…