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IP Core

D16550: Configurable UART with FIFO

Soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A

IP Core

D16750: Configurable UART with FIFO

Soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750.

IP Core

USB 2.0 Device with FIFO Interface (USB20HF)

USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.

FAQ

Simulation: Why does my PMI FIFO get a simulation error, "Error! Fifo depth can only be power of 2!"?

Simulation: The PMI FIFO (First In First Out) simulation model has a check to prevent invalid FIFO depth. This message is meant to provide an accurate model of the generated FIFO. Giving FIFO depths as a power of 2 (such as 512) will prevent this error. Since hardware…

IP Core

DSPI_FIFO: Serial Peripheral Interface - Master/Slave with FIFO

Fully configurable SPI master/slave device

FAQ

Can I bypass the FPGA Bridge FIFO in the LatticeECP2/M PCS block?

The LatticeECP2/M FPGA Bridge FIFO is enabled by default in the IPExpress GUI. If the user wants to bypass the FIFO it can be done by editing the auto-config file(.txt) as:ch#_tx_gear_bypass "1" ch#_rx_gear_bypass "1" Where "#" represents the channel number. The entry is…

FAQ

[MIPI CSI-2/ DSI D-PHY RX]Could you tell me about method to calculate of MIPI Rx IP's FIFO depth?

Solution:There is no specific formula being followed in setting up the packet delay and fifo depth. What is advised is to apply similar concept to rate, time, and distance. Where the goal is to make READ and WRITE run at same speed, or atleast Write side has very small difference with Read…

FAQ

LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?

The Big/Little Endian mode switch will affect the word order when read data bus width and write data bus width are set as different values:Case 1: write data bus width is 36bits and read data bus width is 18bitsFor the Big Endian mode: if write Data[35:0], you will first read out Data[17:0] and then…

FAQ

FIFO for Nexus FPGAs: How does the three FIFO_DC Controller Implementation differs from each other?

1. Controller Implementation = Area-Optimized (HW):Uses a Hardened FIFO controller + Hardened Memory Block for data storage.2. Controller Implementation =Feature-Rich (LUT) ; Implementation type = EBR:Uses a Fabric-implemented FIFO controller + Hardened Memory Block for data storage.3.…

IP Core

USB 2.0 Device Controller IP Core (USB20SF)

USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU

IP Core

UART with FIFOs and Synchronous CPU Interface Core

A standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device

FAQ

For SERDES/PCS-based Lattice devices, can I use the CTC FIFO in the hard PCS even if I connect the PCS to the SGMII/GbE PCS IP?

The answer depends both on device family and data rate:In the case of the LatticeSC device, the user can only use the CTC in the SGMII/GbE PCS IP.In the case of the LatticeECP2M and LatticeECP3 devices, the use of the  hard PCS CTC depends on the mode of operation:You cannot use the PCS CTC when…

IP Core

CSIX Level 1

Archived IP Core supporting ORCA FPGAs - For reference only.

Document

FIFO Memory Modules Release Notes

Release Notes FPGA-RN-02095 1.0 PDF 268.5KB

Document

DCD: D16550: Configurable UART with FIFO

Data Sheet 2.11 PDF 182.6KB

Document

DCD: D16750: Configurable UART with FIFO

Data Sheet 2.11 PDF 183.5KB

IP Core

​​eSPI Target IP Core​

​​Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.​

Webpage

Easy Interfacing to USB

FAQ

Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data.During the time the RX clocks are unstable, the pointers on the PCS  RX FPGA  interface FIFO (RX FIFO) can reach invalid values.When the CDR finally…