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ID: 1008
Case Type: faq
Category: Architecture
Related To: SERDES/PCS
Family: LatticeECP2/M

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Can I bypass the FPGA Bridge FIFO in the LatticeECP2/M PCS block?

The LatticeECP2/M FPGA Bridge FIFO is enabled by default in the IPExpress GUI. If the user wants to bypass the FIFO it can be done by editing the auto-config file(.txt) as:


ch#_tx_gear_bypass "1"


ch#_rx_gear_bypass "1"



Where "#" represents the channel number. The entry is case-insensitive.