The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.
The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (2 16 -1), and producing a 16 x clock for driving the internal transmitter logic. Provisions are also included to use this 16 x clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
The configuration capability allow user to enable or disable during Synthesis process the Modem Control Logic and FIFO's Control Logic, or change the FIFO size. So in applications with area limitation and where the UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources.