Mach-NX – Hardware Security for Programmable System Control

Supports 384-bit Cryptography and MCTP-SPDM

Cyber Resilient System Control – Builds on Lattice secure control leadership by addressing evolving PFR requirements. Includes immutable Secure Enclave to enable HW RoT & 384-bit cryptography.

Dynamic End-to-End Firmware Protection – Provides real-time firmware protection with nanosecond response time to block malicious activity on the system bus.

Rapidly Customizable – Easily configure security features in RISC-V environment with Lattice Propel. Develop NIST SP 800-193 compliant PFR solutions in days.

Features

  • Up to 8.4K LC of user logic, 2669 kbits of user flash memory and dual boot flash feature
  • Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC
  • Configuration of PFR and security functions through Lattice Propel simplifies developer experience
  • Highly reliable. Low power and 3X better SER performance to comparable CMOS technologies

Jump to

Family Table

Mach-NX Device Selection Guide
Features LFMNX-50
User LCs 8400
Distributed RAM (kbits) 73
EBR SRAM (kbits) 432
UFM (kbits) 1064 / 26691
Number of PLLs 2
Hardened Security Functions2
Configurable PFR 1
Secure Enclave 1
SoC Hardened Functions
I2C 2
SPI 1
Timer / Counter 1
Oscillator 1
On-chip Dual-boot Yes3
Core Vcc - 1.0V Yes
Temperature
Commercial Yes
Industrial Yes

1. When dual-boot is disabled, image space can be repurposed as extra UFM.
2. 40K LCs equivalent design
3. For user logic

0.8 mm Pitch Packages & Total I/O Count

LFMNX-50
256-ball caBGA (14 x 14 mm) 200
484-ball caBGA (19 x 19 mm) 379

Block Diagram

Mach-NX Architecture

  • Up to 8.4K LCs user logic, up to 2669 kbits of user flash memory and dual boot flash feature
  • Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Secure enclave supports 384-bit cryptography

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Mach-NX SFB Hardware Usage Guide
FPGA-TN-02222 1.0 10/7/2021 PDF 1.9 MB
Mach-NX sysIO Usage Guide
FPGA-TN-02233 1.0 12/8/2020 PDF 1.1 MB
Mach-NX PFR and SFB Architecture Usage Guide
FPGA-TN-02230 0.83 9/6/2021 PDF 1.9 MB
Mach-NX sysCLOCK PLL Design and Usage Guide
FPGA-TN-02215 1.0 9/22/2021 PDF 2 MB
Mach-NX Dual Boot Usage Guide
FPGA-TN-02229 1.0 8/31/2021 PDF 508.6 KB
Memory Usage Guide for Mach-NX Devices
FPGA-TN-02236 1.0 12/7/2020 PDF 7.7 MB
Mach-NX Hardware Checklist
FPGA-TN-02235 1.1 8/30/2021 PDF 803.9 KB
Mach-NX Programming and Configuration Usage Guide
FPGA-TN-02231 1.0 5/26/2021 PDF 2.4 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.3 6/23/2021 PDF 776.5 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.7 9/21/2021 PDF 7.6 MB
Implementing High Speed Interfaces with Mach-NX
FPGA-TN-02234 1.0 12/8/2020 PDF 2.2 MB
Mach-NX Device Family Data Sheet
FPGA-DS-02084 .80 12/7/2020 PDF 3.3 MB
Mach-NX FCBGA484 Pinout
FPGA-SC-02020 1.0 9/8/2021 CSV 16.6 KB
Package Diagrams
FPGA-DS-02053 6.6 9/28/2021 PDF 8.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Mach-NX Device Family Data Sheet
FPGA-DS-02084 .80 12/7/2020 PDF 3.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Mach-NX SFB Hardware Usage Guide
FPGA-TN-02222 1.0 10/7/2021 PDF 1.9 MB
Mach-NX sysIO Usage Guide
FPGA-TN-02233 1.0 12/8/2020 PDF 1.1 MB
Mach-NX PFR and SFB Architecture Usage Guide
FPGA-TN-02230 0.83 9/6/2021 PDF 1.9 MB
Mach-NX sysCLOCK PLL Design and Usage Guide
FPGA-TN-02215 1.0 9/22/2021 PDF 2 MB
Mach-NX Dual Boot Usage Guide
FPGA-TN-02229 1.0 8/31/2021 PDF 508.6 KB
Memory Usage Guide for Mach-NX Devices
FPGA-TN-02236 1.0 12/7/2020 PDF 7.7 MB
Mach-NX Hardware Checklist
FPGA-TN-02235 1.1 8/30/2021 PDF 803.9 KB
Mach-NX Programming and Configuration Usage Guide
FPGA-TN-02231 1.0 5/26/2021 PDF 2.4 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.3 6/23/2021 PDF 776.5 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.7 9/21/2021 PDF 7.6 MB
Implementing High Speed Interfaces with Mach-NX
FPGA-TN-02234 1.0 12/8/2020 PDF 2.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Mach-NX FCBGA484 Pinout
FPGA-SC-02020 1.0 9/8/2021 CSV 16.6 KB
Package Diagrams
FPGA-DS-02053 6.6 9/28/2021 PDF 8.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
OrCAD Symbols
FPGA-SC-02019 12/8/2020 OLB 48.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Product Selector Guide
I0211 32.0 10/1/2021 PDF 11.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Mach-NX White Paper
1.0 12/8/2020 PDF 228.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LFMNX-50
FPGA-MD-02011 1.14 12/8/2020 ZIP 18.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Mach-NX Device Family Delphi Models
FPGA-MD-02021 1.0 3/2/2021 ZIP 171.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] LFMNX-50
FPGA-MD-02012 1.0 2/25/2021 ZIP 15.4 MB

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