Mach-NX

Hardware Security for Programmable System Control

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Related Products

Related Applications

Cyber Resilient System Control – Builds on Lattice secure control leadership by addressing evolving PFR requirements. Includes immutable Secure Enclave to enable HW RoT & 384-bit cryptography.

Dynamic End-to-End Firmware Protection – Provides real-time firmware protection with nanosecond response time to block malicious activity on the system bus.

Rapidly Customizable – Easily configure security features in RISC-V environment with Lattice Propel. Develop NIST SP 800-193 compliant PFR solutions in days.

Features

  • Up to 8.4K LC of user logic, 2669 kbits of user flash memory and dual boot flash feature
  • Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC
  • Configuration of PFR and security functions through Lattice Propel simplifies developer experience
  • Highly reliable. Low power and 3X better SER performance to comparable CMOS technologies

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Mach-NX Device Selection Guide
Features LFMNX-50
User LCs 8400
Distributed RAM (kbits) 73
EBR SRAM (kbits) 432
UFM (kbits) 1064 / 26691
Number of PLLs 2
Hardened Security Functions2
Configurable PFR 1
Secure Enclave 1
SoC Hardened Functions
I2C 2
SPI 1
Timer / Counter 1
Oscillator 1
On-chip Dual-boot Yes3
Core Vcc - 1.0V Yes
Temperature
Commercial Yes
Industrial Yes

1. When dual-boot is disabled, image space can be repurposed as extra UFM.
2. 40K LCs equivalent design
3. For user logic

0.8 mm Pitch Packages & Total I/O Count

LFMNX-50
256-ball fcCSP (14 x 14 mm) 188
484-ball fcBGA (19 x 19 mm) 378

Block Diagram

Mach-NX Architecture Expand Image

Mach-NX Architecture

  • Up to 8.4K LCs user logic, up to 2669 kbits of user flash memory and dual boot flash feature
  • Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Secure enclave supports 384-bit cryptography

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