What are the possible delay variations expected with the transmit and receive SERDES?
When using the LatticeSC/M PCS/SERDES there will always be a slight difference in the delay through the transmit and receive path. This delay can be different at each power up. Here is why.
Receive Path
The receive signal will need to go through the CDR which will have +/- 1UI of delay variation when trying to lock to the signal. If the word aligner is used then there will be up to a full 10 or 8 bit word -1 UI of delay variation as the word aligner attempts to lock onto the proper parallel word. Crossing into the FPGA fabric a phase compensation FIFO will add +/- 1 parallel word clock cycle if using an 8-bit interface or +/- 2 clock cycles if you are using a 16-bit interface.
Transmit Path
On the transmit side the same phase compensation FIFO is used to cross from the FPGA fabric into the PCS/SERDES. This FIFO will add +/- 1 parallel word clock cycle if using an 8-bit interface or +/- 2 clock cycles if you are using a 16-bit interface. The serializer uses a free running counter to take the parallel word and peel off bits for serialization. Depending on the value of this counter based on the presented parallel word it will add up to 10 or 8 bit word -1 UI of delay (similar to the word aligner).