CAS latency cannot be change while configuring the DDR1 or DDR2 SDRAM memory controller IP via IPexpress.
However, once you generate the MICO32 with the DDR memory controller IP peripheral from Mico System Builder (MSB) , a Verilog file that initializes the CAS latency is generated as part of the project files. You can edit this Verilog file to modify the CAS latency.
Under \Hardware\MSB\components\wb_ddr$x_ctl_v$y\rtl\verilog lies a wb_ddr$x_intf.v file.
( $x depends on whether DDR1 or DDR2 is used , and $y refers to the IP revision number)
You can modify the wb_ddr$x_intf.v file to use a different CAS latency (CL) value.
The generated file should have the line :
addr <= #UDLY 'h31; //BL:2 CL:3
Bit6 down to Bit4 set the CL value according to the JEDEC spec.
The default value above specifies a CAS latency of 3.
To change CL to 2, edit the line as follows:
addr <= #UDLY 'h21; //BL:2 CL:2
The CL value cannot be changed in real time after bitstream generation.
Note that rerunning through the MICO32/DDR memory controller generation flow will re-generate this file and overwrite any user edits...