Definition:
The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL.
For some applications users may use this LOCK signal as a flag or control signal when the PLL is unlocked. But this status signal should be used carefully if users are using this signal for control or state machine input.
During operation, if the input clock or feedback signals to the PLL become invalid, the PLL will lose lock. However, when the input clock completely stops, the LOCK output will remain in its last state which can be a high signal, since it is internally registered by this clock. It is recommended to assert PLL RST to re-synchronize the PLL to the reference clock. The LOCK signal is available to the FPGA routing to implement generation of RST.
Refers details to the application note:
http://www.latticesemi.com/lit/docs/technotes/tn1103.pdf