Propel Builder: Why RISC-V project simulation encountered below error message? ** Error (suppressible): xxx/lib/latticesemi.com/ip/cpu0/2.2.0/rtl/cpu0.sv(515): (vlog-2388) '' already declared in this scope () at ().
Description:
User may encounter cpu.v compilation error in Model Sim if directly run the Simulation Wizard from Radiant software for any RISC-V project.
Solution:
The correct method is to leverage the verification tool provided in Propel Builder to create a verification project, which setup a proper RISC-V simulation environment.
User may refer to FPGA-UG-02143 chapter 2.3 for more information.
2.3. Verification Project Design Flow
2.3.1. Creating a Verification Project