PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI (without using GUI)?
Description: There are some parameters that cannot be configured using LMMI.
Example, in these 2 parameters:
a) Target Link Speed \u2013 this is possible. The LMMI write needs to happen before PHY out of reset
b) Use TLP Interface \u2013 this is not possible as this info is needed during IP generation so the PCIe soft RTL will know how to expose the interface at top level.