Description:
The PLL LOCK signal is not asserted HIGH immediately after ECP5 enters user mode, as PLL has to see valid clock input for specific duration before it asserts the LOCK signal.
The PLL gets active to see the valid clock input only after the device enters user mode. The PLL LOCK signal is not asserted before the device enters into user mode.
User can refer to the tlock (PLL Lock-in time) value from the device datasheet.