Reveal Logic Analyzer can be used for On-Chip Debug even if the targeted device is a JTAG chain with multiple devices.
Use ispVM to define the JTAG chain and the position of the targeted device in the chain. Then, save the chain (.xcf) file and upload the .xcf file into the Reveal Logic Analyzer during project creation.
Some limitations apply.
- Users can only debug one device at a time in a daisy chain.;
- Only one of the bitstreams in a daisy chain can include a Reveal core.
For detailed information on the Reveal Logic Analyzer, go to the ispLEVER Help menu or the Lattice Diamond Help menu. This contains the Reveal Tutorial and the Reveal User Guide which detail how to create the Reveal core and set up the Reveal Logic Analyzer.