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ID: 353
实例类型: faq
分类: Architecture
相关: General Logic
产品系列: All FPGA

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What is the state of FPGA Flip Flop outputs at power-up? The reset pins of my design registers are tied to neither GSR nor LSR.

Even if GSR/LSR are not used in RTL, GSR is always used during bitstream download to reset flip flops up to the point when download is complete.


So the state of a register's Q output is 0 at powerup. This assumes that clock input to the register is at steady state logic low.

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