文章详情

ID: 325
实例类型: faq
分类: Customer Board Design
相关: Board Debug
产品系列: All FPGA

搜索答案数据库

Search Text Image

How can I estimate the pull up and pull down resistors of Lattice's CPLD and FPGA devices?

User can find I/O Active Pull-up Current (Ipu), I/O Active Pull-down Current (Ipd), and the voltage for the I/O ports (e.g., Vccio) in Lattice's data sheets. User can derive the pull up and pull down resistor values by dividing the voltage by the current. User can find Lattice's data sheets at the following location:

Lattice Semiconductor Product List