Article Details

ID: 325
Case Type: faq
Category: Customer Board Design
Related To: Board Debug
Family: All FPGA

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How can I estimate the pull up and pull down resistors of Lattice's CPLD and FPGA devices?

User can find I/O Active Pull-up Current (Ipu), I/O Active Pull-down Current (Ipd), and the voltage for the I/O ports (e.g., Vccio) in Lattice's data sheets. User can derive the pull up and pull down resistor values by dividing the voltage by the current. User can find Lattice's data sheets at the following location:

Lattice Semiconductor Product List