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ID: 2604
实例类型: faq
分类: Lattice IP/Reference Design
相关: DDR3 SDRAM Controller
产品系列: LatticeECP3

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DDR3 IP:  The generated DDR3 IP core includes a DDR3 DIMM (dual in-line memory module) instantiation module (ddr3_dimm_32.v) in the testbench when the selected memory type is On-board Memory. How can I instantiate the DDR3 device memory model in my testbench for simulation?

Although the file name includes "dimm", the generated memory
instantiation module such as "ddr3_dimm_32.v" is a memory wrapper
that covers all DDR3 memory configurations including the On-board Memory
type. This wrapper module includes all possible memory configurations
and types including UDIMM, RDIMM, discrete memory with write leveling
and address mirroring considerations. Therefore, it is okay for the user to
use this memory module for the simulation of any generated DDR3 IP core.

If the user does not want to use the memory wrapper file generated under the On-board Memory option, the user can directly instantiate the memory model. They just need to make sure that the ddr3_parameters.vh file is properly included in the testbench. The memory model, ddr3.v, cannot be run without this parameter file.