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ID: 2347
实例类型: faq
分类: Architecture
相关: IO
产品系列: MachXO2

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MachXO2: Why does the Lattice software picks VCCIO bank voltages smaller than 3.3V when all my design IO buffers are of the 3.3V type?

Description:

The situation above can occur when you set your IO buffer HYSTERESIS attribute to NA.


You can normally set your IO buffer HYSTERISIS attribute using one of the three methods shown below:



  • ispLEVER software: 


    1. Start the Design Planner target from the Processes window.

    2. Select View-> Spreadsheet View.

    3. Select the Port Attributes tab from the SpreadShhet View tool.

  • Lattice Diamond software: select Tools-> Spreadsheet View. Then select the Port Assignments tab.

  • LPF file: Use the IOBUF property as shown in the example below:


IOBUF PORT "A_8" IO_TYPE=LVCMOS33 PULLMODE=NONE HYSTERESIS=SMALL;


SLOW is the default HYSTERESIS attribute for 3.3V output and bi-directional buffers. Per software usage mode, as long as the HYSTERESIS attribute on the buffer is set to SMALL or LARGE, the Lattice software tool will set the the corresponding IO bank VCCIO to 3.3V.


However, if you set the HYSTERESIS attribute to NA, then the tool will set the corresponding bank VCCIO to 2.5V or a smaller value. This potentially creates IO voltage conflicts with most of the 3.3V buffers residing on the same bank.


The example below shows a VCCIO conflict on an output buffer as a result of setting the HYSTERESIS attribute to NA on an input buffer residing in the same IO bank:


ERROR - par: Cannot place PIO comp "COM_A_17" on PIO site "A15/PT24B" (I/O bank 0).
ERROR - par: I/O banking rule check failed: Incompatible Vccio -- Bank 0 Vccio=1.5V, while for PIO comp "COM_A_17", Vccio=3.3V.


As a recommendation, set the HYSTERESIS attribute to SMALL (default value), or LARGE for input and bi-directional buffers.